0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; Takashi Kubo; Masaru Haraguchi; Yoshito Nakaoka; Mihoko Akiyama; Yasuhiro Konishi; Hideyuki Ozaki; Tsutomu Yoshihara

doi:10.1109/4.881215

0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.

Original language	English
Pages (from-to)	1680-1689
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	35
Issue number	11
DOIs	https://doi.org/10.1109/4.881215
Publication status	Published - 2000 Nov
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.881215

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Kuge, S., Kato, T., Furutani, K., Kikuda, S., Mitsui, K., Hamamoto, T., Setogawa, J., Hamade, K., Komiya, Y., Kawasaki, S., Kono, T., Amano, T., Kubo, T., Haraguchi, M., Nakaoka, Y., Akiyama, M., Konishi, Y., Ozaki, H., & Yoshihara, T. (2000). 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE Journal of Solid-State Circuits, 35(11), 1680-1689. https://doi.org/10.1109/4.881215

Kuge, S, Kato, T, Furutani, K, Kikuda, S, Mitsui, K, Hamamoto, T, Setogawa, J, Hamade, K, Komiya, Y, Kawasaki, S, Kono, T, Amano, T, Kubo, T, Haraguchi, M, Nakaoka, Y, Akiyama, M, Konishi, Y, Ozaki, H & Yoshihara, T 2000, '0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica', IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1680-1689. https://doi.org/10.1109/4.881215

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abstract = "A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.",

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AU - Kuge, Shigehiro

AU - Kato, Tetsuo

AU - Furutani, Kiyohiro

AU - Kikuda, Shigeru

AU - Mitsui, Katsuyoshi

AU - Hamamoto, Takeshi

AU - Setogawa, Jun

AU - Hamade, Kei

AU - Komiya, Yuichiro

AU - Kawasaki, Satoshi

AU - Kono, Takashi

AU - Amano, Teruhiko

AU - Kubo, Takashi

AU - Haraguchi, Masaru

AU - Nakaoka, Yoshito

AU - Akiyama, Mihoko

AU - Konishi, Yasuhiro

AU - Ozaki, Hideyuki

AU - Yoshihara, Tsutomu

PY - 2000/11

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0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

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