10μW/cm2-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology

M. Tomita; S. Oba; Y. Himeda; R. Yamato; K. Shima; T. Kumada; M. Xu; H. Takezawa; K. Mesaki; K. Tsuda; S. Hashimoto; T. Zhan; H. Zhang; Y. Kamakura; Y. Suzuki; H. Inokawa; H. Ikeda; T. Matsukawa; T. Matsuki; T. Watanabe

doi:10.1109/VLSIT.2018.8510659

10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology

M. Tomita, S. Oba, Y. Himeda, R. Yamato, K. Shima, T. Kumada, M. Xu, H. Takezawa, K. Mesaki, K. Tsuda, S. Hashimoto, T. Zhan, H. Zhang, Y. Kamakura, Y. Suzuki, H. Inokawa, H. Ikeda, T. Matsukawa, T. Matsuki, T. Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm², which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	93-94
Number of pages	2
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510659
Publication status	Published - 2018 Oct 25
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: 2018 Jun 18 → 2018 Jun 22

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Other

Other	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	18/6/18 → 18/6/22

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2018.8510659

Cite this

Tomita, M., Oba, S., Himeda, Y., Yamato, R., Shima, K., Kumada, T., Xu, M., Takezawa, H., Mesaki, K., Tsuda, K., Hashimoto, S., Zhan, T., Zhang, H., Kamakura, Y., Suzuki, Y., Inokawa, H., Ikeda, H., Matsukawa, T., Matsuki, T., & Watanabe, T. (2018). 10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 93-94). Article 8510659 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510659

10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. / Tomita, M.; Oba, S.; Himeda, Y. et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 93-94 8510659 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tomita, M, Oba, S, Himeda, Y, Yamato, R, Shima, K, Kumada, T, Xu, M, Takezawa, H, Mesaki, K, Tsuda, K, Hashimoto, S, Zhan, T, Zhang, H, Kamakura, Y, Suzuki, Y, Inokawa, H, Ikeda, H, Matsukawa, T, Matsuki, T & Watanabe, T 2018, 10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510659, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 93-94, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/6/18. https://doi.org/10.1109/VLSIT.2018.8510659

Tomita M, Oba S, Himeda Y, Yamato R, Shima K, Kumada T et al. 10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 93-94. 8510659. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2018.8510659

@inproceedings{b82e063edcae48b1a52f242a7a4cc7ef,

title = "10μW/cm2-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology",

abstract = "A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.",

author = "M. Tomita and S. Oba and Y. Himeda and R. Yamato and K. Shima and T. Kumada and M. Xu and H. Takezawa and K. Mesaki and K. Tsuda and S. Hashimoto and T. Zhan and H. Zhang and Y. Kamakura and Y. Suzuki and H. Inokawa and H. Ikeda and T. Matsukawa and T. Matsuki and T. Watanabe",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

month = oct,

day = "25",

doi = "10.1109/VLSIT.2018.8510659",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "93--94",

booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",

}

TY - GEN

T1 - 10μW/cm2-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology

AU - Tomita, M.

AU - Oba, S.

AU - Himeda, Y.

AU - Yamato, R.

AU - Shima, K.

AU - Kumada, T.

AU - Xu, M.

AU - Takezawa, H.

AU - Mesaki, K.

AU - Tsuda, K.

AU - Hashimoto, S.

AU - Zhan, T.

AU - Zhang, H.

AU - Kamakura, Y.

AU - Suzuki, Y.

AU - Inokawa, H.

AU - Ikeda, H.

AU - Matsukawa, T.

AU - Matsuki, T.

AU - Watanabe, T.

PY - 2018/10/25

Y1 - 2018/10/25

N2 - A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.

AB - A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.

UR - http://www.scopus.com/inward/record.url?scp=85055366686&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85055366686&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2018.8510659

DO - 10.1109/VLSIT.2018.8510659

M3 - Conference contribution

AN - SCOPUS:85055366686

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 93

EP - 94

BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018

Y2 - 18 June 2018 through 22 June 2018

ER -