1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit

H. Suzuki*, H. Takata, H. Shinohara, E. Teraoka, M. Matsuo, T. Yoshida, H. Sato, N. Honda, N. Masui, T. Shimizu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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