12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Atsushi Muramatsu; Tadashi Yasufuku; Masahiro Nomura; Makoto Takamiya; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1109/ESSCIRC.2011.6044897

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Atsushi Muramatsu^*, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (V_DD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high V_DD (V_DDH) and low V_DD (V_DDL) are supplied to each power domain and either V_DDH or V_DDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single V_DD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.

Original language	English
Title of host publication	ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
Pages	191-194
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2011.6044897
Publication status	Published - 2011 Dec 12
Externally published	Yes
Event	37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland Duration: 2011 Sept 12 → 2011 Sept 16

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Other

Other	37th European Solid-State Circuits Conference, ESSCIRC 2011
Country/Territory	Finland
City	Helsinki
Period	11/9/12 → 11/9/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2011.6044897

Cite this

Muramatsu, A., Yasufuku, T., Nomura, M., Takamiya, M., Shinohara, H., & Sakurai, T. (2011). 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference (pp. 191-194). Article 6044897 (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2011.6044897

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. / Muramatsu, Atsushi; Yasufuku, Tadashi; Nomura, Masahiro et al.
ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 191-194 6044897 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Muramatsu, A, Yasufuku, T, Nomura, M, Takamiya, M, Shinohara, H & Sakurai, T 2011, 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. in ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference., 6044897, European Solid-State Circuits Conference, pp. 191-194, 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, 11/9/12. https://doi.org/10.1109/ESSCIRC.2011.6044897

Muramatsu A, Yasufuku T, Nomura M, Takamiya M, Shinohara H, Sakurai T. 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. In ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. 2011. p. 191-194. 6044897. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2011.6044897

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AB - Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.

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12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

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