120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

Yasushi Terada*, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
PublisherPubl by IEEE
Pages136-137, 315
Publication statusPublished - 1989
Externally publishedYes
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 1989 Feb 151989 Feb 17


OtherIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
CityNew York, NY, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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