120-ns 128K × 8-bit/64K × 16-bit CMOS EEPROMs

Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Masanori Hayashikoshi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara

doi:10.1109/JSSC.1989.572588

120-ns 128K × 8-bit/64K × 16-bit CMOS EEPROMs

Yasushi Terada^*, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

A 1-Mb CMOS full-featured EEPROM using a 1.0-μm triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mb EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient error checking and correction scheme is developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8 × 8.0 μm², and the chip size is 7.73 × 11.83 mm². The device is organized as either 128K × 8 or 64K × 16 by via-hole mask options. A 256-byte/128-word-page-mode programming is implemented.

Original language	English
Pages (from-to)	1244-1249
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1989.572588
Publication status	Published - 1989 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1989.572588

Cite this

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title = "120-ns 128K × 8-bit/64K × 16-bit CMOS EEPROMs",

abstract = "A 1-Mb CMOS full-featured EEPROM using a 1.0-μm triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mb EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient error checking and correction scheme is developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8 × 8.0 μm2, and the chip size is 7.73 × 11.83 mm2. The device is organized as either 128K × 8 or 64K × 16 by via-hole mask options. A 256-byte/128-word-page-mode programming is implemented.",

author = "Yasushi Terada and Kazuo Kobayashi and Takeshi Nakayama and Masanori Hayashikoshi and Yoshikazu Miyawaki and Natsuo Ajika and Hideaki Arima and Takayuki Matsukawa and Tsutomu Yoshihara",

year = "1989",

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AU - Terada, Yasushi

AU - Kobayashi, Kazuo

AU - Nakayama, Takeshi

AU - Hayashikoshi, Masanori

AU - Miyawaki, Yoshikazu

AU - Ajika, Natsuo

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

PY - 1989/10

Y1 - 1989/10

N2 - A 1-Mb CMOS full-featured EEPROM using a 1.0-μm triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mb EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient error checking and correction scheme is developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8 × 8.0 μm2, and the chip size is 7.73 × 11.83 mm2. The device is organized as either 128K × 8 or 64K × 16 by via-hole mask options. A 256-byte/128-word-page-mode programming is implemented.

AB - A 1-Mb CMOS full-featured EEPROM using a 1.0-μm triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mb EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient error checking and correction scheme is developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8 × 8.0 μm2, and the chip size is 7.73 × 11.83 mm2. The device is organized as either 128K × 8 or 64K × 16 by via-hole mask options. A 256-byte/128-word-page-mode programming is implemented.

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120-ns 128K × 8-bit/64K × 16-bit CMOS EEPROMs

Abstract

ASJC Scopus subject areas

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