12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1109/ISLPED.2011.5993630

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics

Hiroshi Fuketa^*, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

Contention-less flip-flops (CLFF's) and separated power supply voltages (V_DD) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling V_DD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.

Original language	English
Title of host publication	IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages	163-168
Number of pages	6
DOIs	https://doi.org/10.1109/ISLPED.2011.5993630
Publication status	Published - 2011 Sept 19
Externally published	Yes
Event	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan Duration: 2011 Aug 1 → 2011 Aug 3

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Country/Territory	Japan
City	Fukuoka
Period	11/8/1 → 11/8/3

Keywords

flip-flop
subthreshold circuit
variations

ASJC Scopus subject areas

Engineering(all)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISLPED.2011.5993630

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Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2011). 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics. In IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 (pp. 163-168). Article 5993630 (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1109/ISLPED.2011.5993630

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics. / Fuketa, Hiroshi; Hirairi, Koji; Yasufuku, Tadashi et al.
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. p. 163-168 5993630 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fuketa, H, Hirairi, K, Yasufuku, T, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2011, 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics. in IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011., 5993630, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 163-168, 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011, Fukuoka, Japan, 11/8/1. https://doi.org/10.1109/ISLPED.2011.5993630

Fuketa H, Hirairi K, Yasufuku T, Takamiya M, Nomura M, Shinohara H et al. 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics. In IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. p. 163-168. 5993630. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1109/ISLPED.2011.5993630

Fuketa, Hiroshi ; Hirairi, Koji ; Yasufuku, Tadashi et al. / 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V_DD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V_DD between flip-flops and combinational logics. IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. pp. 163-168 (Proceedings of the International Symposium on Low Power Electronics and Design).

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abstract = "Contention-less flip-flops (CLFF's) and separated power supply voltages (VDD) between flip-flops (FF's) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65-nm CMOS process. Measurement results of fabricated chips show that the proposed CLFF reduces the minimum operating voltage of IU's by 64mV on average. By scaling VDD from 1.2V to 310mV with the proposed CLFF, the maximum energy efficiency of 1835GOPS/W and the highest energy efficiency increase of 12.7 times are achieved.",

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