1.2GFLOPS neural network chip exhibiting fast convergence

Yoshikazu Kondo; Yuichi Koshiba; Yutaka Arima; Mitsuhiro Murasaki; Tuyoshi Yamada; Hiroyuki Amishiro; Hirofumi Shinohara; Hakuro Mori

1.2GFLOPS neural network chip exhibiting fast convergence

Yoshikazu Kondo^*, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hirofumi Shinohara, Hakuro Mori

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	Anon
Publisher	Publ by IEEE
Pages	218-219
Number of pages	2
ISBN (Print)	0780318455
Publication status	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1994 Feb 16 → 1994 Feb 18

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Other

Other	Proceedings of the 1994 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	94/2/16 → 94/2/18

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Kondo, Y., Koshiba, Y., Arima, Y., Murasaki, M., Yamada, T., Amishiro, H., Shinohara, H., & Mori, H. (1994). 1.2GFLOPS neural network chip exhibiting fast convergence. In Anon (Ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 218-219). (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Publ by IEEE.

1.2GFLOPS neural network chip exhibiting fast convergence. / Kondo, Yoshikazu; Koshiba, Yuichi; Arima, Yutaka et al.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Anon. Publ by IEEE, 1994. p. 218-219 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kondo, Y, Koshiba, Y, Arima, Y, Murasaki, M, Yamada, T, Amishiro, H, Shinohara, H & Mori, H 1994, 1.2GFLOPS neural network chip exhibiting fast convergence. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Publ by IEEE, pp. 218-219, Proceedings of the 1994 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 94/2/16.

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abstract = "This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.",

author = "Yoshikazu Kondo and Yuichi Koshiba and Yutaka Arima and Mitsuhiro Murasaki and Tuyoshi Yamada and Hiroyuki Amishiro and Hirofumi Shinohara and Hakuro Mori",

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AU - Shinohara, Hirofumi

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AB - This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.

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1.2GFLOPS neural network chip exhibiting fast convergence

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