14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama; Kyoya Takano; Shuhei Amakawa; Takeshi Yoshida; Minoru Fujishima

doi:10.1109/RFIT.2016.7578218

14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

Original language	English
Title of host publication	RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509012350
DOIs	https://doi.org/10.1109/RFIT.2016.7578218
Publication status	Published - 2016 Sept 27
Externally published	Yes
Event	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan, Province of China Duration: 2016 Aug 24 → 2016 Aug 26

Publication series

Name	RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology

Other

Other	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
Country/Territory	Taiwan, Province of China
City	Taipei
Period	16/8/24 → 16/8/26

Keywords

Bias optimization
circuit modeling
figure of merit
reduction of measurement

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/RFIT.2016.7578218

Cite this

Katayama, K., Takano, K., Amakawa, S., Yoshida, T., & Fujishima, M. (2016). 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. In RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology Article 7578218 (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2016.7578218

14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. / Katayama, Kosuke; Takano, Kyoya; Amakawa, Shuhei et al.
RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 2016. 7578218 (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Katayama, K, Takano, K, Amakawa, S, Yoshida, T & Fujishima, M 2016, 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. in RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology., 7578218, RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016, Taipei, Taiwan, Province of China, 16/8/24. https://doi.org/10.1109/RFIT.2016.7578218

Katayama K, Takano K, Amakawa S, Yoshida T, Fujishima M. 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. In RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc. 2016. 7578218. (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology). doi: 10.1109/RFIT.2016.7578218

Katayama, Kosuke ; Takano, Kyoya ; Amakawa, Shuhei et al. / 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 2016. (RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology).

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abstract = "In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.",

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AB - In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

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14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Abstract

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Keywords

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