16Mb DRAM/SOI Technologies for Sub-1V Operation

T. Oashi; T. Eimori; F. Morishita; T. Iwamatsu; Y. Yamaguchi; F. Okuda; K. Shimomura; H. Shimano; N. Sakashita; K. Arimoto; Y. Inoue; S. Komori; M. Inuishi; T. Nishimura; H. Miyoshi

doi:10.1109/IEDM.1996.554057

16Mb DRAM/SOI Technologies for Sub-1V Operation

T. Oashi, T. Eimori, F. Morishita, T. Iwamatsu, Y. Yamaguchi, F. Okuda, K. Shimomura^*, H. Shimano^*, N. Sakashita^*, K. Arimoto, Y. Inoue, S. Komori^*, M. Inuishi, T. Nishimura, H. Miyoshi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

11 Citations (Scopus)

Abstract

Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET’s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.

Original language	English
Pages (from-to)	609-612
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.1996.554057
Publication status	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 1996 Dec 8 → 1996 Dec 11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.1996.554057

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Oashi, T., Eimori, T., Morishita, F., Iwamatsu, T., Yamaguchi, Y., Okuda, F., Shimomura, K., Shimano, H., Sakashita, N., Arimoto, K., Inoue, Y., Komori, S., Inuishi, M., Nishimura, T., & Miyoshi, H. (1996). 16Mb DRAM/SOI Technologies for Sub-1V Operation. Technical Digest - International Electron Devices Meeting, IEDM, 609-612. https://doi.org/10.1109/IEDM.1996.554057

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title = "16Mb DRAM/SOI Technologies for Sub-1V Operation",

abstract = "Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET{\textquoteright}s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.",

author = "T. Oashi and T. Eimori and F. Morishita and T. Iwamatsu and Y. Yamaguchi and F. Okuda and K. Shimomura and H. Shimano and N. Sakashita and K. Arimoto and Y. Inoue and S. Komori and M. Inuishi and T. Nishimura and H. Miyoshi",

note = "Publisher Copyright: {\textcopyright} 1996 IEEE; Proceedings of the 1996 IEEE International Electron Devices Meeting ; Conference date: 08-12-1996 Through 11-12-1996",

year = "1996",

doi = "10.1109/IEDM.1996.554057",

language = "English",

pages = "609--612",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

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TY - JOUR

T1 - 16Mb DRAM/SOI Technologies for Sub-1V Operation

AU - Oashi, T.

AU - Eimori, T.

AU - Morishita, F.

AU - Iwamatsu, T.

AU - Yamaguchi, Y.

AU - Okuda, F.

AU - Shimomura, K.

AU - Shimano, H.

AU - Sakashita, N.

AU - Arimoto, K.

AU - Inoue, Y.

AU - Komori, S.

AU - Inuishi, M.

AU - Nishimura, T.

AU - Miyoshi, H.

PY - 1996

Y1 - 1996

N2 - Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET’s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.

AB - Extra low voltage D M S O 1technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET’s, and (4)reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOIwas successfullyrealized and functional operation was obtained at very low supply voltage below 1v.

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DO - 10.1109/IEDM.1996.554057

M3 - Conference article

AN - SCOPUS:0030422230

SN - 0163-1918

SP - 609

EP - 612

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

T2 - Proceedings of the 1996 IEEE International Electron Devices Meeting

Y2 - 8 December 1996 through 11 December 1996

ER -

16Mb DRAM/SOI Technologies for Sub-1V Operation

Abstract

ASJC Scopus subject areas

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