17-bit oversampling D-to-A conversion technology using multistage noise shaping

Yasuyuki Matsuya; Kuniharu Uchimura; Atsushi Iwata; Takao Kaneko

doi:10.1109/4.34079

17-bit oversampling D-to-A conversion technology using multistage noise shaping

Yasuyuki Matsuya^*, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

47 Citations (Scopus)

Abstract

A description is given of a highly stable, triple-integration two-stage noise-shaping technique and a precise differential pulse-width modulation (PWM) output method which permits greater accuracy in monolithic audio digital-to-analog (D-to-A) converters (DACs) without trimming. Based on these techniques and using 1.5-μm CMOS technology, a 17-bit 20-kHz-bandwidth DAC LSI chip with digital filters was developed. A signal-to-noise ratio (S/(N + THD)) of 101 dB and a total harmonic distortion (THD) of 0.0007% at full-scale input were obtained.

Original language	English
Pages (from-to)	969-975
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/4.34079
Publication status	Published - 1989
Externally published	Yes
Event	Symposium on VLSI Circuits - Tokyo, Japan Duration: 1988 Aug 22 → 1988 Aug 24

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.34079

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title = "17-bit oversampling D-to-A conversion technology using multistage noise shaping",

abstract = "A description is given of a highly stable, triple-integration two-stage noise-shaping technique and a precise differential pulse-width modulation (PWM) output method which permits greater accuracy in monolithic audio digital-to-analog (D-to-A) converters (DACs) without trimming. Based on these techniques and using 1.5-μm CMOS technology, a 17-bit 20-kHz-bandwidth DAC LSI chip with digital filters was developed. A signal-to-noise ratio (S/(N + THD)) of 101 dB and a total harmonic distortion (THD) of 0.0007% at full-scale input were obtained.",

author = "Yasuyuki Matsuya and Kuniharu Uchimura and Atsushi Iwata and Takao Kaneko",

year = "1989",

doi = "10.1109/4.34079",

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note = "Symposium on VLSI Circuits ; Conference date: 22-08-1988 Through 24-08-1988",

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T1 - 17-bit oversampling D-to-A conversion technology using multistage noise shaping

AU - Matsuya, Yasuyuki

AU - Uchimura, Kuniharu

AU - Iwata, Atsushi

AU - Kaneko, Takao

PY - 1989

Y1 - 1989

N2 - A description is given of a highly stable, triple-integration two-stage noise-shaping technique and a precise differential pulse-width modulation (PWM) output method which permits greater accuracy in monolithic audio digital-to-analog (D-to-A) converters (DACs) without trimming. Based on these techniques and using 1.5-μm CMOS technology, a 17-bit 20-kHz-bandwidth DAC LSI chip with digital filters was developed. A signal-to-noise ratio (S/(N + THD)) of 101 dB and a total harmonic distortion (THD) of 0.0007% at full-scale input were obtained.

AB - A description is given of a highly stable, triple-integration two-stage noise-shaping technique and a precise differential pulse-width modulation (PWM) output method which permits greater accuracy in monolithic audio digital-to-analog (D-to-A) converters (DACs) without trimming. Based on these techniques and using 1.5-μm CMOS technology, a 17-bit 20-kHz-bandwidth DAC LSI chip with digital filters was developed. A signal-to-noise ratio (S/(N + THD)) of 101 dB and a total harmonic distortion (THD) of 0.0007% at full-scale input were obtained.

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DO - 10.1109/4.34079

M3 - Conference article

AN - SCOPUS:0024716952

SN - 0018-9200

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EP - 975

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

T2 - Symposium on VLSI Circuits

Y2 - 22 August 1988 through 24 August 1988

ER -

17-bit oversampling D-to-A conversion technology using multistage noise shaping

Abstract

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