24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits

Tadashi Yasufuku; Koji Hirairi; Yu Pu; Yun Fei Zheng; Ryo Takahashi; Masato Sasaki; Hiroshi Fuketa; Atsushi Muramatsu; Masahiro Nomura; Hirofumi Shinohara; Makoto Takamiya; Takayasu Sakurai

doi:10.1109/ISQED.2012.6187553

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V _DDmin limited ultra low voltage logic circuits

Tadashi Yasufuku^*, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

A post-fabrication dual supply voltage (V _DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V _DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V _DD below V _DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC'S circuit fabricated in 65nm CMOS. The layout of DES CODEC'S is divided into 64 V _DD domains and each domain size is 54μm x 63.2μm. High V _DD (V _DDH) or low V _DD (V _DDL) is applied to each domain and the selection of V _DD's is performed based on multiple built-in self tests. V _DDH is selected in V _DDmin-critical domains, while V _DDL is selected in V _DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V _DDH =437mV, and V _DDL =397mV.

Original language	English
Title of host publication	Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
Pages	586-591
Number of pages	6
DOIs	https://doi.org/10.1109/ISQED.2012.6187553
Publication status	Published - 2012 Jul 16
Externally published	Yes
Event	13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States Duration: 2012 Mar 19 → 2012 Mar 21

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	13th International Symposium on Quality Electronic Design, ISQED 2012
Country/Territory	United States
City	Santa Clara, CA
Period	12/3/19 → 12/3/21

Keywords

Low voltage logic circuit
dual supply voltage
fine-grain power supply voltage
low power

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISQED.2012.6187553

Cite this

Yasufuku, T., Hirairi, K., Pu, Y., Zheng, Y. F., Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M., & Sakurai, T. (2012). 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V _DDmin limited ultra low voltage logic circuits. In Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012 (pp. 586-591). Article 6187553 (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2012.6187553

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V _DDmin limited ultra low voltage logic circuits. / Yasufuku, Tadashi; Hirairi, Koji; Pu, Yu et al.
Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. 2012. p. 586-591 6187553 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yasufuku, T, Hirairi, K, Pu, Y, Zheng, YF, Takahashi, R, Sasaki, M, Fuketa, H, Muramatsu, A, Nomura, M, Shinohara, H, Takamiya, M & Sakurai, T 2012, 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V _DDmin limited ultra low voltage logic circuits. in Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012., 6187553, Proceedings - International Symposium on Quality Electronic Design, ISQED, pp. 586-591, 13th International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, United States, 12/3/19. https://doi.org/10.1109/ISQED.2012.6187553

Yasufuku T, Hirairi K, Pu Y, Zheng YF, Takahashi R, Sasaki M et al. 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V _DDmin limited ultra low voltage logic circuits. In Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. 2012. p. 586-591. 6187553. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2012.6187553

Yasufuku, Tadashi ; Hirairi, Koji ; Pu, Yu et al. / 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V _DDmin limited ultra low voltage logic circuits. Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. 2012. pp. 586-591 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

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