3.3 V-only 16 Mb DINOR flash memory

Shin ichi Kobayashi; Masaaki Mihara; Yoshikazu Miyawaki; Motoharu Ishii; Tomoshi Futatsuya; Akira Hosogane; Atsushi Ohba; Yasushi Terada; Natsuo Ajika; Yuichi Kunori; Kojiro Yuzuriha; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara; Yuji Uji

3.3 V-only 16 Mb DINOR flash memory

Shin ichi Kobayashi^*, Masaaki Mihara, Yoshikazu Miyawaki, Motoharu Ishii, Tomoshi Futatsuya, Akira Hosogane, Atsushi Ohba, Yasushi Terada, Natsuo Ajika, Yuichi Kunori, Kojiro Yuzuriha, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara, Yuji Uji

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

29 Citations (Scopus)

Abstract

A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm ². 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publisher	IEEE
Volume	38
Publication status	Published - 1995 Feb
Externally published	Yes
Event	Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1995 Feb 15 → 1995 Feb 17

Other

Other	Proceedings of the 1995 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	95/2/15 → 95/2/17

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Kobayashi, SI, Mihara, M, Miyawaki, Y, Ishii, M, Futatsuya, T, Hosogane, A, Ohba, A, Terada, Y, Ajika, N, Kunori, Y, Yuzuriha, K, Hatanaka, M, Miyoshi, H, Yoshihara, T & Uji, Y 1995, 3.3 V-only 16 Mb DINOR flash memory. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 38, IEEE, Proceedings of the 1995 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 95/2/15.

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title = "3.3 V-only 16 Mb DINOR flash memory",

abstract = "A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost. ",

author = "Kobayashi, {Shin ichi} and Masaaki Mihara and Yoshikazu Miyawaki and Motoharu Ishii and Tomoshi Futatsuya and Akira Hosogane and Atsushi Ohba and Yasushi Terada and Natsuo Ajika and Yuichi Kunori and Kojiro Yuzuriha and Masahiro Hatanaka and Hirokazu Miyoshi and Tsutomu Yoshihara and Yuji Uji",

year = "1995",

month = feb,

language = "English",

volume = "38",

booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "IEEE",

note = "Proceedings of the 1995 IEEE International Solid-State Circuits Conference ; Conference date: 15-02-1995 Through 17-02-1995",

}

TY - GEN

T1 - 3.3 V-only 16 Mb DINOR flash memory

AU - Kobayashi, Shin ichi

AU - Mihara, Masaaki

AU - Miyawaki, Yoshikazu

AU - Ishii, Motoharu

AU - Futatsuya, Tomoshi

AU - Hosogane, Akira

AU - Ohba, Atsushi

AU - Terada, Yasushi

AU - Ajika, Natsuo

AU - Kunori, Yuichi

AU - Yuzuriha, Kojiro

AU - Hatanaka, Masahiro

AU - Miyoshi, Hirokazu

AU - Yoshihara, Tsutomu

AU - Uji, Yuji

PY - 1995/2

Y1 - 1995/2

N2 - A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

AB - A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

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M3 - Conference contribution

AN - SCOPUS:0029255454

VL - 38

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

PB - IEEE

T2 - Proceedings of the 1995 IEEE International Solid-State Circuits Conference

Y2 - 15 February 1995 through 17 February 1995

ER -

3.3 V-only 16 Mb DINOR flash memory

Abstract

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ASJC Scopus subject areas

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