34ns 256Mb DRAM with boosted sense-ground scheme

Mikio Asakura; Tsukasa Ohishi; Masaki Tsukude; Shigeki Tomishima; Hideto Hidaka; Kazutami Anmoto; Kazuyasu Fujishima; Takahisa Eimori; Yoshikazu Ohno; Tadashi Nishimura; Masatoshi Yasunaga; Takashi Kondon; Shin ichi Satoh; Tsutomu Yoshihara; Kiyoshi Demizu

34ns 256Mb DRAM with boosted sense-ground scheme

Mikio Asakura^*, Tsukasa Ohishi, Masaki Tsukude, Shigeki Tomishima, Hideto Hidaka, Kazutami Anmoto, Kazuyasu Fujishima, Takahisa Eimori, Yoshikazu Ohno, Tadashi Nishimura, Masatoshi Yasunaga, Takashi Kondon, Shin ichi Satoh, Tsutomu Yoshihara, Kiyoshi Demizu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

This paper describes boosted sense-ground (BSG) scheme extends the data retention time of a 256Mb DRAM. This scheme features a `L' bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs). A chip-scale package (CSP) technique is used to reduce package size to near chip size. A perspective view of the package is shown. The experimental 256Mb DRAM uses 0.25μm CMOS technology with triple-level metal. cs is 25fF with a 0. 72μm² cell. The chip is 304mm². The power supply is regulated internally to 2.5V.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	Anon
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	140-141
Number of pages	2
ISBN (Print)	0780318455
Publication status	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1994 Feb 16 → 1994 Feb 18

Other

Other	Proceedings of the 1994 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	94/2/16 → 94/2/18

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Engineering(all)

Cite this

Asakura, M., Ohishi, T., Tsukude, M., Tomishima, S., Hidaka, H., Anmoto, K., Fujishima, K., Eimori, T., Ohno, Y., Nishimura, T., Yasunaga, M., Kondon, T., Satoh, S. I., Yoshihara, T., & Demizu, K. (1994). 34ns 256Mb DRAM with boosted sense-ground scheme. In Anon (Ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 140-141). Publ by IEEE.

Asakura, M, Ohishi, T, Tsukude, M, Tomishima, S, Hidaka, H, Anmoto, K, Fujishima, K, Eimori, T, Ohno, Y, Nishimura, T, Yasunaga, M, Kondon, T, Satoh, SI, Yoshihara, T & Demizu, K 1994, 34ns 256Mb DRAM with boosted sense-ground scheme. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, Piscataway, NJ, United States, pp. 140-141, Proceedings of the 1994 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 94/2/16.

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abstract = "This paper describes boosted sense-ground (BSG) scheme extends the data retention time of a 256Mb DRAM. This scheme features a `L' bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs). A chip-scale package (CSP) technique is used to reduce package size to near chip size. A perspective view of the package is shown. The experimental 256Mb DRAM uses 0.25μm CMOS technology with triple-level metal. cs is 25fF with a 0. 72μm2 cell. The chip is 304mm2. The power supply is regulated internally to 2.5V.",

author = "Mikio Asakura and Tsukasa Ohishi and Masaki Tsukude and Shigeki Tomishima and Hideto Hidaka and Kazutami Anmoto and Kazuyasu Fujishima and Takahisa Eimori and Yoshikazu Ohno and Tadashi Nishimura and Masatoshi Yasunaga and Takashi Kondon and Satoh, {Shin ichi} and Tsutomu Yoshihara and Kiyoshi Demizu",

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AU - Asakura, Mikio

AU - Ohishi, Tsukasa

AU - Tsukude, Masaki

AU - Tomishima, Shigeki

AU - Hidaka, Hideto

AU - Anmoto, Kazutami

AU - Fujishima, Kazuyasu

AU - Eimori, Takahisa

AU - Ohno, Yoshikazu

AU - Nishimura, Tadashi

AU - Yasunaga, Masatoshi

AU - Kondon, Takashi

AU - Satoh, Shin ichi

AU - Yoshihara, Tsutomu

AU - Demizu, Kiyoshi

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AB - This paper describes boosted sense-ground (BSG) scheme extends the data retention time of a 256Mb DRAM. This scheme features a `L' bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs). A chip-scale package (CSP) technique is used to reduce package size to near chip size. A perspective view of the package is shown. The experimental 256Mb DRAM uses 0.25μm CMOS technology with triple-level metal. cs is 25fF with a 0. 72μm2 cell. The chip is 304mm2. The power supply is regulated internally to 2.5V.

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BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

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CY - Piscataway, NJ, United States

T2 - Proceedings of the 1994 IEEE International Solid-State Circuits Conference

Y2 - 16 February 1994 through 18 February 1994

ER -

34ns 256Mb DRAM with boosted sense-ground scheme

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