4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

Hirofumi Shinohara; Kenji Anami; Katsuki Ichinose; Tomehisa Wada; Yoshio Kohno; Yuji Kawai; Yoichi Akasaka; Shinpei Kayano

4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

Hirofumi Shinohara^*, Kenji Anami, Katsuki Ichinose, Tomehisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

Original language	English
Pages (from-to)	62-63
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 1985
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.",

abstract = "Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.",

author = "Hirofumi Shinohara and Kenji Anami and Katsuki Ichinose and Tomehisa Wada and Yoshio Kohno and Yuji Kawai and Yoichi Akasaka and Shinpei Kayano",

year = "1985",

language = "English",

pages = "62--63",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - 4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

AU - Shinohara, Hirofumi

AU - Anami, Kenji

AU - Ichinose, Katsuki

AU - Wada, Tomehisa

AU - Kohno, Yoshio

AU - Kawai, Yuji

AU - Akasaka, Yoichi

AU - Kayano, Shinpei

PY - 1985

Y1 - 1985

N2 - Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

AB - Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

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M3 - Conference article

AN - SCOPUS:0022207549

SN - 0193-6530

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JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -

4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

Abstract

ASJC Scopus subject areas

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