50 ns video signal processor

Shin ichi Nakagawa; Hideyuki Terane; Tetsuya Matsumura; Hiroshi Segawa; Masahiko Yoshimoto; Hirofumi Shinohara; Shu ichi Kato; Atsushi Maeda; Yasutaka Horiba; Hideo Ohira; Yoshi aki Katoh; Mamoru Iwatsuki; Kin ya Tabuchi

50 ns video signal processor

Shin ichi Nakagawa^*, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Masahiko Yoshimoto, Hirofumi Shinohara, Shu ichi Kato, Atsushi Maeda, Yasutaka Horiba, Hideo Ohira, Yoshi aki Katoh, Mamoru Iwatsuki, Kin ya Tabuchi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

9 Citations (Scopus)

Abstract

A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

Original language	English
Pages (from-to)	168-169, 328
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	32
Publication status	Published - 1989 Dec 1
Externally published	Yes
Event	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA Duration: 1989 Feb 15 → 1989 Feb 17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "50 ns video signal processor",

abstract = "A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.",

author = "Nakagawa, {Shin ichi} and Hideyuki Terane and Tetsuya Matsumura and Hiroshi Segawa and Masahiko Yoshimoto and Hirofumi Shinohara and Kato, {Shu ichi} and Atsushi Maeda and Yasutaka Horiba and Hideo Ohira and Katoh, {Yoshi aki} and Mamoru Iwatsuki and Tabuchi, {Kin ya}",

year = "1989",

month = dec,

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language = "English",

volume = "32",

pages = "168--169, 328",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) ; Conference date: 15-02-1989 Through 17-02-1989",

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T1 - 50 ns video signal processor

AU - Nakagawa, Shin ichi

AU - Terane, Hideyuki

AU - Matsumura, Tetsuya

AU - Segawa, Hiroshi

AU - Yoshimoto, Masahiko

AU - Shinohara, Hirofumi

AU - Kato, Shu ichi

AU - Maeda, Atsushi

AU - Horiba, Yasutaka

AU - Ohira, Hideo

AU - Katoh, Yoshi aki

AU - Iwatsuki, Mamoru

AU - Tabuchi, Kin ya

PY - 1989/12/1

Y1 - 1989/12/1

N2 - A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

AB - A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0-μm double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.

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M3 - Conference article

AN - SCOPUS:0024887013

SN - 0193-6530

VL - 32

SP - 168-169, 328

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)

Y2 - 15 February 1989 through 17 February 1989

ER -

50 ns video signal processor

Abstract

ASJC Scopus subject areas

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