50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

Takao Kaneko; Hironori Yamauchi; Atsushi Iwata

50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

Takao Kaneko^*, Hironori Yamauchi, Atsushi Iwata

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Citations (Scopus)

Abstract

A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

Original language	English
Pages (from-to)	401-404
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication status	Published - 1986
Externally published	Yes

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

Cite this

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title = "50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.",

abstract = "A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.",

author = "Takao Kaneko and Hironori Yamauchi and Atsushi Iwata",

year = "1986",

language = "English",

pages = "401--404",

journal = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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AU - Kaneko, Takao

AU - Yamauchi, Hironori

AU - Iwata, Atsushi

PY - 1986

Y1 - 1986

N2 - A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

AB - A high-speed programmable digital signal processor (DSP) VLSI with an 18-bit floating-point architecture and a 32-bit microinstruction has been fabricated using 1. 2- mu m CMOS technology. The device contains 280K transistors and executes every floating-point operation within a 50-ns machine-cycle. The architecture differs from that of the digital speech signal processor reported previously in its high-speed parallel pipeline structure, 16K-byte on-chip microprogram ROM, floating-point ALU capable of 50-ns operation, and enhanced DSP instruction set.

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M3 - Conference article

AN - SCOPUS:0022908735

SN - 0736-7791

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JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

ER -

50NS FLOATING-POINT SIGNAL PROCESSOR VLSI.

Abstract

ASJC Scopus subject areas

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