5V only 1 Tr. 256K EEPROM with page mode erase

Takeshi Nakayama; Yoshikazu Miyawaki; Kazuo Kobayashi; Yasushi Terada; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara

5V only 1 Tr. 256K EEPROM with page mode erase

Takeshi Nakayama^*, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

Original language	English
Title of host publication	1988 Symp VLSI Circuits Dig Tech Pap
Editors	Anon
Pages	81-82
Number of pages	2
Publication status	Published - 1988
Externally published	Yes
Event	1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan Duration: 1988 Aug 22 → 1988 Aug 24

Other

Other	1988 Symposium on VLSI Circuits - Digest of Technical Papers
City	Tokyo, Japan
Period	88/8/22 → 88/8/24

ASJC Scopus subject areas

Engineering(all)

Cite this

@inproceedings{7316e7eab8864dcd879137e2925790a5,

title = "5V only 1 Tr. 256K EEPROM with page mode erase",

abstract = "A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.",

author = "Takeshi Nakayama and Yoshikazu Miyawaki and Kazuo Kobayashi and Yasushi Terada and Hideaki Arima and Takayuki Matsukawa and Tsutomu Yoshihara",

year = "1988",

language = "English",

pages = "81--82",

editor = "Anon",

booktitle = "1988 Symp VLSI Circuits Dig Tech Pap",

note = "1988 Symposium on VLSI Circuits - Digest of Technical Papers ; Conference date: 22-08-1988 Through 24-08-1988",

}

TY - GEN

T1 - 5V only 1 Tr. 256K EEPROM with page mode erase

AU - Nakayama, Takeshi

AU - Miyawaki, Yoshikazu

AU - Kobayashi, Kazuo

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

PY - 1988

Y1 - 1988

N2 - A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

AB - A 5-V only one transistor page-erase-type 256K EEPROM which is erased and programmed by Fowler-Nordheim tunneling current and is program-inhibited by applying a program-inhibiting voltage to drains and the control gates is described. The number of parity bits for error checking and correction (ECC) is five per two bytes, which are controlled by the LB signal. LB is the lowest address input. The total number of memory cells is 88% of that for byte erase-type EEPROMs, and the chip size is substantially reduced. The device has a fast two-byte serial access mode.

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UR - http://www.scopus.com/inward/citedby.url?scp=0024175625&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024175625

SP - 81

EP - 82

BT - 1988 Symp VLSI Circuits Dig Tech Pap

A2 - Anon, null

T2 - 1988 Symposium on VLSI Circuits - Digest of Technical Papers

Y2 - 22 August 1988 through 24 August 1988

ER -

5V only 1 Tr. 256K EEPROM with page mode erase

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