60 ns 3.3 V 16 Mb DRAM

Kazutami Arimoto*, Kazuyasu Fujishima, Yoshio Matsuda, Tsukasa Oishi, Masaki Tsukude, Wataru Wakamiya, Shin ichi Satoh, Michihiro Yamada, Tsutomu Yoshihara, Takao Nakano

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)


The authors describe a single 3.3-V, 16-Mb DRAM (dynamic RAM) fabricated in a 0.5-μm, twin-well CMOS technology and packaged in a 400-mil small-outline J-leaded package. The design features are an array architecture based on the twisted-bit-line (TBL) technique and a multipurpose register (MPR) enabling an effective line mode test (LMT), copy write, and high-speed cache access capability. Under typical conditions at V cc = 3.3 V, a row-address-strobe access time of 60 ns was obtained. Features of the RAM are summarized.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
PublisherPubl by IEEE
Pages244-245, 352
Publication statusPublished - 1989
Externally publishedYes
EventIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA
Duration: 1989 Feb 151989 Feb 17


OtherIEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
CityNew York, NY, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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