60 ns access 32 kByte 3-transistor flash for low power embedded applications

Tamio Ikehashi; Junichiro Noda; Kenichi Imamiya; Masaaki Ichikawa; Akira Iwata; Takuya Futatsuyama

60 ns access 32 kByte 3-transistor flash for low power embedded applications

Tamio Ikehashi^*, Junichiro Noda, Kenichi Imamiya, Masaaki Ichikawa, Akira Iwata, Takuya Futatsuyama

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

3 Citations (Scopus)

Abstract

3-Transistor Flash (3-Tr) is a new flash memory suited for embedded application. The 32 kByte memory cell has the low power erase/program characteristic of NAND flash, and the size of the cell fabricated in a 0.4 um NAND flash technology is 4.36 μm². This is about 1/8 of the EEPROM cells size with the same design rule. Two circuit technologies, a low power sensing scheme and a double stage boosting scheme, are proposed. The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during program mode.

Original language	English
Pages	162-165
Number of pages	4
Publication status	Published - 2000 Jan 1
Externally published	Yes
Event	2000 Symposium on VLSI Circuits - Honolulu, HI, USA Duration: 2000 Jun 15 → 2000 Jun 17

Conference

Conference	2000 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	00/6/15 → 00/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "60 ns access 32 kByte 3-transistor flash for low power embedded applications",

abstract = "3-Transistor Flash (3-Tr) is a new flash memory suited for embedded application. The 32 kByte memory cell has the low power erase/program characteristic of NAND flash, and the size of the cell fabricated in a 0.4 um NAND flash technology is 4.36 μm2. This is about 1/8 of the EEPROM cells size with the same design rule. Two circuit technologies, a low power sensing scheme and a double stage boosting scheme, are proposed. The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during program mode.",

author = "Tamio Ikehashi and Junichiro Noda and Kenichi Imamiya and Masaaki Ichikawa and Akira Iwata and Takuya Futatsuyama",

year = "2000",

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T1 - 60 ns access 32 kByte 3-transistor flash for low power embedded applications

AU - Ikehashi, Tamio

AU - Noda, Junichiro

AU - Imamiya, Kenichi

AU - Ichikawa, Masaaki

AU - Iwata, Akira

AU - Futatsuyama, Takuya

PY - 2000/1/1

Y1 - 2000/1/1

N2 - 3-Transistor Flash (3-Tr) is a new flash memory suited for embedded application. The 32 kByte memory cell has the low power erase/program characteristic of NAND flash, and the size of the cell fabricated in a 0.4 um NAND flash technology is 4.36 μm2. This is about 1/8 of the EEPROM cells size with the same design rule. Two circuit technologies, a low power sensing scheme and a double stage boosting scheme, are proposed. The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during program mode.

AB - 3-Transistor Flash (3-Tr) is a new flash memory suited for embedded application. The 32 kByte memory cell has the low power erase/program characteristic of NAND flash, and the size of the cell fabricated in a 0.4 um NAND flash technology is 4.36 μm2. This is about 1/8 of the EEPROM cells size with the same design rule. Two circuit technologies, a low power sensing scheme and a double stage boosting scheme, are proposed. The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during program mode.

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M3 - Paper

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T2 - 2000 Symposium on VLSI Circuits

Y2 - 15 June 2000 through 17 June 2000

ER -

60 ns access 32 kByte 3-transistor flash for low power embedded applications

Abstract

Conference

ASJC Scopus subject areas

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