80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama; Y. Nishida; H. Oda; J. Tsuchimoto; H. Umeda; A. Teramoto; K. Eikyu; Y. Inoue; M. Inuishi

80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

H. Sayama^*, Y. Nishida, H. Oda, J. Tsuchimoto, H. Umeda, A. Teramoto, K. Eikyu, Y. Inoue, M. Inuishi

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

11 Citations (Scopus)

Abstract

The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.

Original language	English
Pages (from-to)	239-242
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 2000 Dec 10 → 2000 Dec 13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process",

abstract = "The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.",

author = "H. Sayama and Y. Nishida and H. Oda and J. Tsuchimoto and H. Umeda and A. Teramoto and K. Eikyu and Y. Inoue and M. Inuishi",

year = "2000",

language = "English",

pages = "239--242",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

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TY - JOUR

T1 - 80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

AU - Sayama, H.

AU - Nishida, Y.

AU - Oda, H.

AU - Tsuchimoto, J.

AU - Umeda, H.

AU - Teramoto, A.

AU - Eikyu, K.

AU - Inoue, Y.

AU - Inuishi, M.

PY - 2000

Y1 - 2000

N2 - The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.

AB - The fabrication of high drive current CMOSFET with 80 nanometer gate length was discussed. Short channel effects (SCE) and parasitic resistance in sub-0.1 micrometer CMOS were improved with the help of double offset-implanted sourse drain extension and silicon nitride deposition. A drive current of 830/400 micro ampere per nanometer with 2.5 nanometer gate insulator was achieved under 1 nanoampere per micrometer offstate leakage at 1.5V operation with 80 nanometer gate length.

UR - http://www.scopus.com/inward/record.url?scp=0034453528&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034453528&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034453528

SN - 0163-1918

SP - 239

EP - 242

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Abstract

ASJC Scopus subject areas

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