A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

Xingyu Wang; Ruilin Zhang; Yuxin Wang; Kunyang Liu; Xuanzhen Wang; Hirofumi Shinohara

doi:10.1109/VLSI-DAT54769.2022.9768078

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

Xingyu Wang^*, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a latch-based TRNG that achieves high raw entropy generation (>0.9) across wide voltage and temperature (0.31.0 V, -40110 °C) in a single latch-based entropy source by static inverter selection and noise enhancement techniques. In a 130 nm CMOS technology, the TRNG occupies 5343 μm2 and consumes 0.116pJ/bit at 0.3 V including an on-chip Von Neumann post-processing circuit. The crypto-graphically-secure randomness of TRNG's output is verified by NIST SP 800-22 and 800-90B tests. An equivalent 20-year life at 0.3 V, 25°C is confirmed by an accelerated aging test.

Original language	English
Title of host publication	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665409216
DOIs	https://doi.org/10.1109/VLSI-DAT54769.2022.9768078
Publication status	Published - 2022
Event	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, Taiwan, Province of China Duration: 2022 Apr 18 → 2022 Apr 21

Publication series

Name	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	22/4/18 → 22/4/21

Keywords

Aging test
Latch
NIST tests
True random number generator
Von-Neumann post-processing

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/VLSI-DAT54769.2022.9768078

Cite this

Wang, X., Zhang, R., Wang, Y., Liu, K., Wang, X., & Shinohara, H. (2022). A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. In 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT54769.2022.9768078

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. / Wang, Xingyu; Zhang, Ruilin; Wang, Yuxin et al.
2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, X, Zhang, R, Wang, Y, Liu, K, Wang, X & Shinohara, H 2022, A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. in 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, Taiwan, Province of China, 22/4/18. https://doi.org/10.1109/VLSI-DAT54769.2022.9768078

Wang X, Zhang R, Wang Y, Liu K, Wang X, Shinohara H. A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. In 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings). doi: 10.1109/VLSI-DAT54769.2022.9768078

Wang, Xingyu ; Zhang, Ruilin ; Wang, Yuxin et al. / A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).

@inproceedings{507fe9afa0fd45b49bec597d242fbe4b,

title = "A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement",

abstract = "This paper presents a latch-based TRNG that achieves high raw entropy generation (>0.9) across wide voltage and temperature (0.31.0 V, -40110 °C) in a single latch-based entropy source by static inverter selection and noise enhancement techniques. In a 130 nm CMOS technology, the TRNG occupies 5343 μm2 and consumes 0.116pJ/bit at 0.3 V including an on-chip Von Neumann post-processing circuit. The crypto-graphically-secure randomness of TRNG's output is verified by NIST SP 800-22 and 800-90B tests. An equivalent 20-year life at 0.3 V, 25°C is confirmed by an accelerated aging test.",

keywords = "Aging test, Latch, NIST tests, True random number generator, Von-Neumann post-processing",

author = "Xingyu Wang and Ruilin Zhang and Yuxin Wang and Kunyang Liu and Xuanzhen Wang and Hirofumi Shinohara",

note = "Funding Information: ACKNOWLEDGMENT This research is supported by ROHM Co. Ltd, Kitakyushu Foundation for the Advancement of Industry, Science and Technology (FAIS), and JST SPRING, Grant Number JPMJSP2128. Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 ; Conference date: 18-04-2022 Through 21-04-2022",

year = "2022",

doi = "10.1109/VLSI-DAT54769.2022.9768078",

language = "English",

series = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",

}

TY - GEN

T1 - A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

AU - Wang, Xingyu

AU - Zhang, Ruilin

AU - Wang, Yuxin

AU - Liu, Kunyang

AU - Wang, Xuanzhen

AU - Shinohara, Hirofumi

N1 - Funding Information: ACKNOWLEDGMENT This research is supported by ROHM Co. Ltd, Kitakyushu Foundation for the Advancement of Industry, Science and Technology (FAIS), and JST SPRING, Grant Number JPMJSP2128. Publisher Copyright: © 2022 IEEE.

PY - 2022

Y1 - 2022

N2 - This paper presents a latch-based TRNG that achieves high raw entropy generation (>0.9) across wide voltage and temperature (0.31.0 V, -40110 °C) in a single latch-based entropy source by static inverter selection and noise enhancement techniques. In a 130 nm CMOS technology, the TRNG occupies 5343 μm2 and consumes 0.116pJ/bit at 0.3 V including an on-chip Von Neumann post-processing circuit. The crypto-graphically-secure randomness of TRNG's output is verified by NIST SP 800-22 and 800-90B tests. An equivalent 20-year life at 0.3 V, 25°C is confirmed by an accelerated aging test.

AB - This paper presents a latch-based TRNG that achieves high raw entropy generation (>0.9) across wide voltage and temperature (0.31.0 V, -40110 °C) in a single latch-based entropy source by static inverter selection and noise enhancement techniques. In a 130 nm CMOS technology, the TRNG occupies 5343 μm2 and consumes 0.116pJ/bit at 0.3 V including an on-chip Von Neumann post-processing circuit. The crypto-graphically-secure randomness of TRNG's output is verified by NIST SP 800-22 and 800-90B tests. An equivalent 20-year life at 0.3 V, 25°C is confirmed by an accelerated aging test.

KW - Aging test

KW - Latch

KW - NIST tests

KW - True random number generator

KW - Von-Neumann post-processing

UR - http://www.scopus.com/inward/record.url?scp=85130473815&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85130473815&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT54769.2022.9768078

DO - 10.1109/VLSI-DAT54769.2022.9768078

M3 - Conference contribution

AN - SCOPUS:85130473815

T3 - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

BT - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022

Y2 - 18 April 2022 through 21 April 2022

ER -

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement

Abstract

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Keywords

ASJC Scopus subject areas

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