A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement

Ruilin Zhang; Xingyu Wang; Luying Wang; Xinpeng Chen; Fan Yang; Kunyang Liu; Hirofumi Shinohara

doi:10.23919/VLSICircuits52068.2021.9492474

A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement

Ruilin Zhang^*, Xingyu Wang, Luying Wang, Xinpeng Chen, Fan Yang, Kunyang Liu, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3∼1.0 V) and temperature (-20∼100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).

Original language	English
Title of host publication	2021 Symposium on VLSI Circuits, VLSI Circuits 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487796
DOIs	https://doi.org/10.23919/VLSICircuits52068.2021.9492474
Publication status	Published - 2021 Jun 13
Event	35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online Duration: 2021 Jun 13 → 2021 Jun 19

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2021-June

Conference

Conference	35th Symposium on VLSI Circuits, VLSI Circuits 2021
City	Virutal, Online
Period	21/6/13 → 21/6/19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSICircuits52068.2021.9492474

Cite this

Zhang, R., Wang, X., Wang, L., Chen, X., Yang, F., Liu, K., & Shinohara, H. (2021). A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021 Article 9492474 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSICircuits52068.2021.9492474

A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. / Zhang, Ruilin; Wang, Xingyu; Wang, Luying et al.
2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9492474 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, R, Wang, X, Wang, L, Chen, X, Yang, F, Liu, K & Shinohara, H 2021, A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. in 2021 Symposium on VLSI Circuits, VLSI Circuits 2021., 9492474, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Virutal, Online, 21/6/13. https://doi.org/10.23919/VLSICircuits52068.2021.9492474

Zhang R, Wang X, Wang L, Chen X, Yang F, Liu K et al. A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9492474. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSICircuits52068.2021.9492474

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title = "A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement",

abstract = "A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3∼1.0 V) and temperature (-20∼100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).",

author = "Ruilin Zhang and Xingyu Wang and Luying Wang and Xinpeng Chen and Fan Yang and Kunyang Liu and Hirofumi Shinohara",

note = "Funding Information: This research is supported by ROHM Co., Ltd. Publisher Copyright: {\textcopyright} 2021 JSAP.; 35th Symposium on VLSI Circuits, VLSI Circuits 2021 ; Conference date: 13-06-2021 Through 19-06-2021",

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AU - Shinohara, Hirofumi

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N2 - A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3∼1.0 V) and temperature (-20∼100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).

AB - A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3∼1.0 V) and temperature (-20∼100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).

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A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement

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