A 0.3mW 1.4mm2 motion estimation processor for mobile video application

Seiichiro Hiratsuka; Satoshi Goto; Takeshi Ikenaga

doi:10.1109/ASSCC.2006.357862

A 0.3mW 1.4mm² motion estimation processor for mobile video application

Seiichiro Hiratsuka^*, Satoshi Goto, Takeshi Ikenaga

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-μm CMOS technology. 15K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm² chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/sec ME processing.

Original language	English
Pages	103-106
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357862
Publication status	Published - 2006 Dec 1
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 2006 Nov 13 → 2006 Nov 15

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	06/11/13 → 06/11/15

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ASSCC.2006.357862

Cite this

@conference{5b468ed0c1bc409da92684ed60e4480e,

title = "A 0.3mW 1.4mm2 motion estimation processor for mobile video application",

abstract = "Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-μm CMOS technology. 15K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm2 chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/sec ME processing.",

author = "Seiichiro Hiratsuka and Satoshi Goto and Takeshi Ikenaga",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2006.357862",

language = "English",

pages = "103--106",

note = "2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 ; Conference date: 13-11-2006 Through 15-11-2006",

}

TY - CONF

T1 - A 0.3mW 1.4mm2 motion estimation processor for mobile video application

AU - Hiratsuka, Seiichiro

AU - Goto, Satoshi

AU - Ikenaga, Takeshi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-μm CMOS technology. 15K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm2 chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/sec ME processing.

AB - Motion estimation (ME) is a key processing in video encoding systems. Since it requires huge computational complexity, many algorithms and LSI architectures have been proposed to reduce it. Conventional LSIs, however, are not sufficient for mobile applications which require both flexibility and low power dissipation. This paper describes an application specific instruction processor (ASIP) LSI for ME processing. It has a dedicated unit for SAD (sum of absolute difference) operations. By applying our proposed ultra-low ME algorithm named ULCMEA, it can reduce power while keeping high flexibility. A chip capable of operating at 80 MHz was fabricated using TSMC 0.18-μm CMOS technology. 15K logic gates and 32 Kbit SRAM have been integrated into 1.4 mm2 chip. Typical power dissipation is 0.3-mW for QCIF 15 frame/sec ME processing.

UR - http://www.scopus.com/inward/record.url?scp=34250799792&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34250799792&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2006.357862

DO - 10.1109/ASSCC.2006.357862

M3 - Paper

AN - SCOPUS:34250799792

SP - 103

EP - 106

T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -