A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Research output: Contribution to journalArticlepeer-review

71 Citations (Scopus)


A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cell's static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJ's cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

Original languageEnglish
Article number6495490
Pages (from-to)1511-1520
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Issue number6
Publication statusPublished - 2013
Externally publishedYes


  • Break-even time (BET)
  • embedded memory
  • magnetic tunnel junction (MTJ)
  • nonvolatile memory
  • power gating
  • power-off time
  • spin-transfer torque random access memory (STT-RAM)
  • static noise margin (SNM)
  • static random access memory (SRAM)
  • wake-up time

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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