A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Dajiang Zhou; Zongyuan You; Jiayi Zhu; Ji Kong; Yu Hong; Xianmin Chen; Xuewen He; Chen Xu; Hang Zhang; Jinjia Zhou; Ning Deng; Peilin Liu; Satoshi Goto

A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Dajiang Zhou^*, Zongyuan You, Jiayi Zhu, Ji Kong, Yu Hong, Xianmin Chen, Xuewen He, Chen Xu, Hang Zhang, Jinjia Zhou, Ning Deng, Peilin Liu, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.

Original language	English
Title of host publication	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages	262-263
Number of pages	2
Publication status	Published - 2009
Externally published	Yes
Event	2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2009 Jun 16 → 2009 Jun 18

Other

Other	2009 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	09/6/16 → 09/6/18

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

Zhou, D, You, Z, Zhu, J, Kong, J, Hong, Y, Chen, X, He, X, Xu, C, Zhang, H, Zhou, J, Deng, N, Liu, P & Goto, S 2009, A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 5205354, pp. 262-263, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.

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AU - Zhou, Dajiang

AU - You, Zongyuan

AU - Zhu, Jiayi

AU - Kong, Ji

AU - Hong, Yu

AU - Chen, Xianmin

AU - He, Xuewen

AU - Xu, Chen

AU - Zhang, Hang

AU - Zhou, Jinjia

AU - Deng, Ning

AU - Liu, Peilin

AU - Goto, Satoshi

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AB - In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.

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BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

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A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

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ASJC Scopus subject areas

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