A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

Naoko Ono; Mizuki Motoyoshi; Kyoya Takano; Kosuke Katayama; Ryuichi Fujimoto; Minoru Fujishima

doi:10.1109/APMC.2012.6421624

A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

Naoko Ono^*, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10^-8. The transmitter has an output power of -0.05 dBm.

Original language	English
Title of host publication	2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
Pages	439-441
Number of pages	3
DOIs	https://doi.org/10.1109/APMC.2012.6421624
Publication status	Published - 2012 Dec 1
Externally published	Yes
Event	2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, Taiwan, Province of China Duration: 2012 Dec 4 → 2012 Dec 7

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other	2012 Asia-Pacific Microwave Conference, APMC 2012
Country/Territory	Taiwan, Province of China
City	Kaohsiung
Period	12/12/4 → 12/12/7

Keywords

ASK
Millimeter-wave
data rate
receiver
transmitter
wireless

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APMC.2012.6421624

Cite this

Ono, N, Motoyoshi, M, Takano, K, Katayama, K, Fujimoto, R & Fujishima, M 2012, A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology. in 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings., 6421624, Asia-Pacific Microwave Conference Proceedings, APMC, pp. 439-441, 2012 Asia-Pacific Microwave Conference, APMC 2012, Kaohsiung, Taiwan, Province of China, 12/12/4. https://doi.org/10.1109/APMC.2012.6421624

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abstract = "A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.",

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author = "Naoko Ono and Mizuki Motoyoshi and Kyoya Takano and Kosuke Katayama and Ryuichi Fujimoto and Minoru Fujishima",

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AU - Ono, Naoko

AU - Motoyoshi, Mizuki

AU - Takano, Kyoya

AU - Katayama, Kosuke

AU - Fujimoto, Ryuichi

AU - Fujishima, Minoru

PY - 2012/12/1

Y1 - 2012/12/1

N2 - A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.

AB - A 113 GHz 176.4 mW transmitter and receiver chipset using 65 nm CMOS technology is presented. To achieve low power consumption, an amplitude shift keying modulation with a simple circuit is adopted for this chipset, and the transmitter does not have a power amplifier. The power consumptions of the transmitter and receiver are 65.5 and 110.9 mW, respectively. A 2.5 Gbps pseudorandom bit sequence is successfully transferred from the transmitter to the receiver by wireless propagation through a distance of 0.2 m with a bit error rate of less than 10-8. The transmitter has an output power of -0.05 dBm.

KW - ASK

KW - Millimeter-wave

KW - data rate

KW - receiver

KW - transmitter

KW - wireless

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A 113 GHz 176 mW transmitter and receiver chipset using 65 nm CMOS technology

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

Access to Document

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