A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Xiao Peng; Zhixiang Chen; Xiongxin Zhao; Dajiang Zhou; Satoshi Goto

doi:10.1109/ASSCC.2011.6123576

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Xiao Peng^*, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm ² in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.

Original language	English
Title of host publication	2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
Pages	317-320
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2011.6123576
Publication status	Published - 2011
Event	7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju Duration: 2011 Nov 14 → 2011 Nov 16

Other

Other	7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011
City	Jeju
Period	11/11/14 → 11/11/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2011.6123576

Cite this

@inproceedings{1bf4e18a487242d388a1fe4c4fc5c94f,

title = "A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS",

abstract = "Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.",

author = "Xiao Peng and Zhixiang Chen and Xiongxin Zhao and Dajiang Zhou and Satoshi Goto",

year = "2011",

doi = "10.1109/ASSCC.2011.6123576",

language = "English",

isbn = "9781467303989",

pages = "317--320",

booktitle = "2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011",

note = "7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 ; Conference date: 14-11-2011 Through 16-11-2011",

}

TY - GEN

T1 - A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

AU - Peng, Xiao

AU - Chen, Zhixiang

AU - Zhao, Xiongxin

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2011

Y1 - 2011

N2 - Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.

AB - Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.

UR - http://www.scopus.com/inward/record.url?scp=84863057826&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863057826&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2011.6123576

DO - 10.1109/ASSCC.2011.6123576

M3 - Conference contribution

AN - SCOPUS:84863057826

SN - 9781467303989

SP - 317

EP - 320

BT - 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

T2 - 7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011

Y2 - 14 November 2011 through 16 November 2011

ER -

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this