A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Xiao Peng*, Zhixiang Chen, Xiongxin Zhao, Dajiang Zhou, Satoshi Goto

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    22 Citations (Scopus)


    Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24-48 clock cycles per iteration for different code rates. It occupies 3.36 mm 2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.

    Original languageEnglish
    Title of host publication2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
    Number of pages4
    Publication statusPublished - 2011
    Event7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju
    Duration: 2011 Nov 142011 Nov 16


    Other7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering


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