A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Tohru Furuyama, Yousei Nagahama

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


A 12-MHz data-cycle 4-Mb DRAM with pipeline operation has been designed and fabricated using 0.8-μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous [formula omitted] cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the [formula omitted] cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95-ns [formula omitted] cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAM's.

Original languageEnglish
Pages (from-to)479-483
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 1991 Apr
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation'. Together they form a unique fingerprint.

Cite this