A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell

Takashi Ohsawa; Tomoki Higashi; Katsuyuki Fujita; Kosuke Hatsuda; Nobuyuki Ikumi; Tomoaki Shino; Hiroomi Nakajima; Yoshihiro Minami; Naoki Kusunoki; Atsushi Sakamoto; Jun Nishimura; Takeshi Hamamoto; Shuso Fujii

A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell

Takashi Ohsawa^*, Tomoki Higashi, Katsuyuki Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Tomoaki Shino, Hiroomi Nakajima, Yoshihiro Minami, Naoki Kusunoki, Atsushi Sakamoto, Jun Nishimura, Takeshi Hamamoto, Shuso Fujii

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

A 128Mbit FBRAM using the floating body cell(FBC) the size of 0.17μm²(6.24F² with F-0.165μm) was successfully fabricated and a high bit yield(∼99.999%) was obtained.

Original language	English
Title of host publication	2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	180-181
Number of pages	2
Publication status	Published - 2006 Dec 1
Externally published	Yes
Event	2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: 2006 Jun 15 → 2006 Jun 17

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2006 Symposium on VLSI Circuits, VLSIC
Country/Territory	United States
City	Honolulu, HI
Period	06/6/15 → 06/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Ohsawa, T., Higashi, T., Fujita, K., Hatsuda, K., Ikumi, N., Shino, T., Nakajima, H., Minami, Y., Kusunoki, N., Sakamoto, A., Nishimura, J., Hamamoto, T., & Fujii, S. (2006). A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell. In 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 180-181). Article 1705369 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell. / Ohsawa, Takashi; Higashi, Tomoki; Fujita, Katsuyuki et al.
2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. 2006. p. 180-181 1705369 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohsawa, T, Higashi, T, Fujita, K, Hatsuda, K, Ikumi, N, Shino, T, Nakajima, H, Minami, Y, Kusunoki, N, Sakamoto, A, Nishimura, J, Hamamoto, T & Fujii, S 2006, A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell. in 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 1705369, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 180-181, 2006 Symposium on VLSI Circuits, VLSIC, Honolulu, HI, United States, 06/6/15.

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abstract = "A 128Mbit FBRAM using the floating body cell(FBC) the size of 0.17μm2(6.24F2 with F-0.165μm) was successfully fabricated and a high bit yield(∼99.999%) was obtained.",

author = "Takashi Ohsawa and Tomoki Higashi and Katsuyuki Fujita and Kosuke Hatsuda and Nobuyuki Ikumi and Tomoaki Shino and Hiroomi Nakajima and Yoshihiro Minami and Naoki Kusunoki and Atsushi Sakamoto and Jun Nishimura and Takeshi Hamamoto and Shuso Fujii",

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AU - Ikumi, Nobuyuki

AU - Shino, Tomoaki

AU - Nakajima, Hiroomi

AU - Minami, Yoshihiro

AU - Kusunoki, Naoki

AU - Sakamoto, Atsushi

AU - Nishimura, Jun

AU - Hamamoto, Takeshi

AU - Fujii, Shuso

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BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers

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A 128Mb floating body RAM(FBRAM) on SOI with multi-averaging scheme of dummy cell

Abstract

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ASJC Scopus subject areas

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