A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

S. Moriwaki; Y. Yamamoto; A. Kawasumi; T. Suzuki; S. Miyano; T. Sakurai; H. Shinohara

doi:10.1109/VLSIC.2012.6243789

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

S. Moriwaki^*, Y. Yamamoto, A. Kawasumi, T. Suzuki, S. Miyano, T. Sakurai, H. Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.

Original language	English
Title of host publication	2012 Symposium on VLSI Circuits, VLSIC 2012
Pages	60-61
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243789
Publication status	Published - 2012
Externally published	Yes
Event	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States Duration: 2012 Jun 13 → 2012 Jun 15

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2012 Symposium on VLSI Circuits, VLSIC 2012
Country/Territory	United States
City	Honolulu, HI
Period	12/6/13 → 12/6/15

Keywords

6T
SRAM
charge-share

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2012.6243789

Cite this

Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Miyano, S., Sakurai, T., & Shinohara, H. (2012). A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. In 2012 Symposium on VLSI Circuits, VLSIC 2012 (pp. 60-61). Article 6243789 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243789

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. / Moriwaki, S.; Yamamoto, Y.; Kawasumi, A. et al.
2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 60-61 6243789 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Moriwaki, S, Yamamoto, Y, Kawasumi, A, Suzuki, T, Miyano, S, Sakurai, T & Shinohara, H 2012, A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. in 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243789, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 60-61, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 12/6/13. https://doi.org/10.1109/VLSIC.2012.6243789

@inproceedings{8768affaa4354c7db13dd8fad9b251ec,

title = "A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges",

abstract = "1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.",

keywords = "6T, SRAM, charge-share",

author = "S. Moriwaki and Y. Yamamoto and A. Kawasumi and T. Suzuki and S. Miyano and T. Sakurai and H. Shinohara",

year = "2012",

doi = "10.1109/VLSIC.2012.6243789",

language = "English",

isbn = "9781467308458",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "60--61",

booktitle = "2012 Symposium on VLSI Circuits, VLSIC 2012",

note = "2012 Symposium on VLSI Circuits, VLSIC 2012 ; Conference date: 13-06-2012 Through 15-06-2012",

}

TY - GEN

T1 - A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

AU - Moriwaki, S.

AU - Yamamoto, Y.

AU - Kawasumi, A.

AU - Suzuki, T.

AU - Miyano, S.

AU - Sakurai, T.

AU - Shinohara, H.

PY - 2012

Y1 - 2012

N2 - 1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.

AB - 1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.

KW - 6T

KW - SRAM

KW - charge-share

UR - http://www.scopus.com/inward/record.url?scp=84866607086&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866607086&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2012.6243789

DO - 10.1109/VLSIC.2012.6243789

M3 - Conference contribution

AN - SCOPUS:84866607086

SN - 9781467308458

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 60

EP - 61

BT - 2012 Symposium on VLSI Circuits, VLSIC 2012

T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012

Y2 - 13 June 2012 through 15 June 2012

ER -

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this