A 1.41 W H.264/AVC real-time encoder soc for HDTV1080P

Zhenyu Liu*, Yang Song, Ming Shao, Shen Li, Ngfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

46 Citations (Scopus)


A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5Gbps 64Mb System-in-Silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.1.8μm CMOS technology, the SoC core occupies 27.1 mm2 die area and consumes 1.41W at 200MHz in typical work conditions.

Original languageEnglish
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2007 Dec 1
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: 2007 Jun 142007 Jun 16

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2007 Symposium on VLSI Circuits, VLSIC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


Dive into the research topics of 'A 1.41 W H.264/AVC real-time encoder soc for HDTV1080P'. Together they form a unique fingerprint.

Cite this