A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang; Fule Li; Yasuaki Inoue

doi:10.1109/ICCCAS.2006.285108

A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

Shuaiqi Wang^*, Fule Li, Yasuaki Inoue

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

Original language	English
Title of host publication	2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings
Pages	2176-2180
Number of pages	5
Volume	4
DOIs	https://doi.org/10.1109/ICCCAS.2006.285108
Publication status	Published - 2006
Event	2006 International Conference on Communications, Circuits and Systems, ICCCAS - Guilin Duration: 2006 Jun 25 → 2006 Jun 28

Other

Other	2006 International Conference on Communications, Circuits and Systems, ICCCAS
City	Guilin
Period	06/6/25 → 06/6/28

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ICCCAS.2006.285108

Cite this

Wang, S, Li, F & Inoue, Y 2006, A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle. in 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings. vol. 4, 4064355, pp. 2176-2180, 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Guilin, 06/6/25. https://doi.org/10.1109/ICCCAS.2006.285108

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abstract = "This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.",

author = "Shuaiqi Wang and Fule Li and Yasuaki Inoue",

year = "2006",

doi = "10.1109/ICCCAS.2006.285108",

language = "English",

isbn = "0780395840",

volume = "4",

pages = "2176--2180",

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AU - Wang, Shuaiqi

AU - Li, Fule

AU - Inoue, Yasuaki

PY - 2006

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N2 - This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

AB - This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs' conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

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BT - 2006 International Conference on Communications, Circuits and Systems, ICCCAS, Proceedings

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A 15-bit 10-msample/s pipelined A/D converter based on incomplete settling principle

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