A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Yimeng Zhang; Leona Okamura; Nan Wang; Tsutomu Yoshihara

doi:10.1109/SOCDC.2010.5682955

A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Yimeng Zhang^*, Leona Okamura, Nan Wang, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

Original language	English
Title of host publication	2010 International SoC Design Conference, ISOCC 2010
Pages	127-130
Number of pages	4
DOIs	https://doi.org/10.1109/SOCDC.2010.5682955
Publication status	Published - 2010
Event	2010 International SoC Design Conference, ISOCC 2010 - Incheon Duration: 2010 Nov 22 → 2010 Nov 23

Other

Other	2010 International SoC Design Conference, ISOCC 2010
City	Incheon
Period	10/11/22 → 10/11/23

ASJC Scopus subject areas

Hardware and Architecture

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10.1109/SOCDC.2010.5682955

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title = "A 160MHz 4-bit pipeline multiplier using charge recovery logic technology",

abstract = "In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.",

author = "Yimeng Zhang and Leona Okamura and Nan Wang and Tsutomu Yoshihara",

year = "2010",

doi = "10.1109/SOCDC.2010.5682955",

language = "English",

isbn = "9781424486335",

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note = "2010 International SoC Design Conference, ISOCC 2010 ; Conference date: 22-11-2010 Through 23-11-2010",

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T1 - A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

AU - Zhang, Yimeng

AU - Okamura, Leona

AU - Wang, Nan

AU - Yoshihara, Tsutomu

PY - 2010

Y1 - 2010

N2 - In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

AB - In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

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DO - 10.1109/SOCDC.2010.5682955

M3 - Conference contribution

AN - SCOPUS:79851484867

SN - 9781424486335

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BT - 2010 International SoC Design Conference, ISOCC 2010

T2 - 2010 International SoC Design Conference, ISOCC 2010

Y2 - 22 November 2010 through 23 November 2010

ER -

A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

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