A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

Yimeng Zhang; Mengshu Huang; Nan Wang; Satoshi Goto; Tsutomu Yoshihara

doi:10.1109/ASSCC.2011.6123640

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

Yimeng Zhang^*, Mengshu Huang, Nan Wang, Satoshi Goto, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.

Original language	English
Title of host publication	2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
Pages	213-216
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2011.6123640
Publication status	Published - 2011
Event	7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju Duration: 2011 Nov 14 → 2011 Nov 16

Other

Other	7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011
City	Jeju
Period	11/11/14 → 11/11/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASSCC.2011.6123640

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Zhang, Y, Huang, M, Wang, N, Goto, S & Yoshihara, T 2011, A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic. in 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011., 6123640, pp. 213-216, 7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, 11/11/14. https://doi.org/10.1109/ASSCC.2011.6123640

@inproceedings{5c1d8f6dedc84a87b2eb9bebd569c2b7,

title = "A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic",

abstract = "This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.",

author = "Yimeng Zhang and Mengshu Huang and Nan Wang and Satoshi Goto and Tsutomu Yoshihara",

year = "2011",

doi = "10.1109/ASSCC.2011.6123640",

language = "English",

isbn = "9781467303989",

pages = "213--216",

booktitle = "2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011",

note = "7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 ; Conference date: 14-11-2011 Through 16-11-2011",

}

TY - GEN

T1 - A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

AU - Zhang, Yimeng

AU - Huang, Mengshu

AU - Wang, Nan

AU - Goto, Satoshi

AU - Yoshihara, Tsutomu

PY - 2011

Y1 - 2011

N2 - This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.

AB - This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.

UR - http://www.scopus.com/inward/record.url?scp=84863015155&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863015155&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2011.6123640

DO - 10.1109/ASSCC.2011.6123640

M3 - Conference contribution

AN - SCOPUS:84863015155

SN - 9781467303989

SP - 213

EP - 216

BT - 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

T2 - 7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011

Y2 - 14 November 2011 through 16 November 2011

ER -

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

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