A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

Toshihiko Yoshimasu; Mengchu Fang; Tsuyoshi Sugiura

doi:10.1587/transfun.2020GCP0012

A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

Toshihiko Yoshimasu^*, Mengchu Fang, Tsuyoshi Sugiura

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

Original language	English
Pages (from-to)	477-483
Number of pages	7
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E104A
Issue number	2
DOIs	https://doi.org/10.1587/transfun.2020GCP0012
Publication status	Published - 2021 Feb 1

Keywords

Adaptive bias
Adaptive load
CMOS SOI
High back-off efficiency
Stacked-FET

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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10.1587/transfun.2020GCP0012

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A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. / Yoshimasu, Toshihiko; Fang, Mengchu; Sugiura, Tsuyoshi.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E104A, No. 2, 01.02.2021, p. 477-483.

Research output: Contribution to journal › Article › peer-review

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abstract = "This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.",

keywords = "Adaptive bias, Adaptive load, CMOS SOI, High back-off efficiency, Stacked-FET",

author = "Toshihiko Yoshimasu and Mengchu Fang and Tsuyoshi Sugiura",

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N1 - Funding Information: The authors would like to thank GLOBALFOUNDRIES for chip fabrication and continuous support. This work is supported by VLSI Design and Education Center (VDEC), Uni- versity of Tokyo in collaboration with Cadence Design Systems, Inc., Menter Graphics, Inc., and Keysight Technologies Japan, Ltd. Publisher Copyright: Copyright © 2021 The Institute of Electronics, Information and Communication Engineers

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N2 - This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

AB - This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5 dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0 V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0 dB.

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KW - Stacked-FET

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A 26-GHz-band high back-off efficiency stacked-FET power amplifier IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI

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Keywords

ASJC Scopus subject areas

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