A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS

Tsuyoshi Sugiura; Cuilin Chen; Toshihiko Yoshimasu

doi:10.1109/APMC46564.2019.9038626

A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS

Tsuyoshi Sugiura, Cuilin Chen, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between-2 dBm and 7 dBm has been realized.

Original language	English
Title of host publication	Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1700-1702
Number of pages	3
ISBN (Electronic)	9781728135175
DOIs	https://doi.org/10.1109/APMC46564.2019.9038626
Publication status	Published - 2019 Dec
Event	2019 IEEE Asia-Pacific Microwave Conference, APMC 2019 - Singapore, Singapore Duration: 2019 Dec 10 → 2019 Dec 13

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC
Volume	2019-December

Conference

Conference	2019 IEEE Asia-Pacific Microwave Conference, APMC 2019
Country/Territory	Singapore
City	Singapore
Period	19/12/10 → 19/12/13

Keywords

Adaptive bias
Adaptively controlled load
High efficiency
SOI CMOS

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/APMC46564.2019.9038626

Cite this

Sugiura, T., Chen, C., & Yoshimasu, T. (2019). A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS. In Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019 (pp. 1700-1702). [9038626] (Asia-Pacific Microwave Conference Proceedings, APMC; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APMC46564.2019.9038626

A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS. / Sugiura, Tsuyoshi; Chen, Cuilin; Yoshimasu, Toshihiko.
Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 1700-1702 9038626 (Asia-Pacific Microwave Conference Proceedings, APMC; Vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sugiura, T, Chen, C & Yoshimasu, T 2019, A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS. in Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019., 9038626, Asia-Pacific Microwave Conference Proceedings, APMC, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., pp. 1700-1702, 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019, Singapore, Singapore, 19/12/10. https://doi.org/10.1109/APMC46564.2019.9038626

Sugiura T, Chen C, Yoshimasu T. A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS. In Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 1700-1702. 9038626. (Asia-Pacific Microwave Conference Proceedings, APMC). doi: 10.1109/APMC46564.2019.9038626

Sugiura, Tsuyoshi ; Chen, Cuilin ; Yoshimasu, Toshihiko. / A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS. Proceedings of the 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 1700-1702 (Asia-Pacific Microwave Conference Proceedings, APMC).

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title = "A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS",

abstract = "This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between-2 dBm and 7 dBm has been realized.",

keywords = "Adaptive bias, Adaptively controlled load, High efficiency, SOI CMOS",

author = "Tsuyoshi Sugiura and Cuilin Chen and Toshihiko Yoshimasu",

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N2 - This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between-2 dBm and 7 dBm has been realized.

AB - This paper presents a 26 GHz band high efficiency power amplifier (PA) IC with adaptively controlled load and bias conditions. An adaptively controlled load matching circuit cooperating with an adaptive bias circuit is proposed to achieve a high efficiency PA IC in a broad range of input power. The chip of PA IC is fabricated using 40-nm silicon on insulator (SOI) CMOS process and evaluated on wafer. The fabricated PA IC has shown a peak PAE of 40.2% and a saturation output power (Psat) of 20.5 dBm with a 4.0 V applied voltage on Vdd at 26GHz. A PAE of over 35% at an input power between-2 dBm and 7 dBm has been realized.

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A 26-GHz-band high efficiency stacked-FET power amplifier ic with adaptively controlled load and bias circuits in 40-nm SOI CMOS

Abstract

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Keywords

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