Abstract
This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.
| Original language | English |
|---|---|
| Title of host publication | EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-2 |
| Number of pages | 2 |
| Volume | 2017-January |
| ISBN (Electronic) | 9781538629079 |
| DOIs | |
| Publication status | Published - 2017 Dec 1 |
| Event | 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 - Hsinchu, Taiwan, Province of China Duration: 2017 Oct 18 → 2017 Oct 20 |
Other
| Other | 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 |
|---|---|
| Country/Territory | Taiwan, Province of China |
| City | Hsinchu |
| Period | 17/10/18 → 17/10/20 |
Keywords
- Adaptive bias circuit
- Linear power amplifier
- SOI CMOS
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Hardware and Architecture
- Electrical and Electronic Engineering