A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS

Cuilin Chen; Tsuyoshi Sugiura; Toshihiko Yoshimasu

doi:10.1109/RWS.2019.8714268

A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS

Cuilin Chen, Tsuyoshi Sugiura, Toshihiko Yoshimasu

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (g_m3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.

Original language	English
Title of host publication	2019 IEEE Radio and Wireless Symposium, RWS 2019
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538659441
DOIs	https://doi.org/10.1109/RWS.2019.8714268
Publication status	Published - 2019 May 14
Event	2019 IEEE Radio and Wireless Symposium, RWS 2019 - Orlando, United States Duration: 2019 Jan 20 → 2019 Jan 23

Publication series

Name	IEEE Radio and Wireless Symposium, RWS
ISSN (Print)	2164-2958
ISSN (Electronic)	2164-2974

Conference

Conference	2019 IEEE Radio and Wireless Symposium, RWS 2019
Country/Territory	United States
City	Orlando
Period	19/1/20 → 19/1/23

Keywords

5G
Adaptive bias
High efficiency
High linearity
SOI CMOS

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Electrical and Electronic Engineering
Communication

Access to Document

10.1109/RWS.2019.8714268

Cite this

A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS. / Chen, Cuilin; Sugiura, Tsuyoshi; Yoshimasu, Toshihiko.
2019 IEEE Radio and Wireless Symposium, RWS 2019. IEEE Computer Society, 2019. 8714268 (IEEE Radio and Wireless Symposium, RWS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, C, Sugiura, T & Yoshimasu, T 2019, A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS. in 2019 IEEE Radio and Wireless Symposium, RWS 2019., 8714268, IEEE Radio and Wireless Symposium, RWS, IEEE Computer Society, 2019 IEEE Radio and Wireless Symposium, RWS 2019, Orlando, United States, 19/1/20. https://doi.org/10.1109/RWS.2019.8714268

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title = "A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS",

abstract = "This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (gm3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.",

keywords = "5G, Adaptive bias, High efficiency, High linearity, SOI CMOS",

author = "Cuilin Chen and Tsuyoshi Sugiura and Toshihiko Yoshimasu",

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N2 - This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (gm3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.

AB - This paper presents a high efficiency linear stacked FET power amplifier (PA) IC for 5G wireless communication systems. An adaptive bias circuit is used to enhance linearity and back-off efficiency. In addition, third-order trans-conductance component (gm3) is cancelled by multi-cascode structure. The PA IC is designed, fabricated and fully evaluated in 56-nm SOI CMOS. At a supply voltage of 4 V, the PA IC has exhibited an output power of 20.0 dBm and a PAE of 38.1% at 1-dB gain compression point (P1dB). The PAEs at 3 dB and 6 dB back-off from P1dB are 36.2 % and 28.7 %, respectively. The output IP3 of 25.0 dBm is obtained.

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KW - Adaptive bias

KW - High efficiency

KW - High linearity

KW - SOI CMOS

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A 28-GHz-band stacked FET linear power amplifier IC with 36.2 % PAE at 3-dB back-off from P1dB in 56-nm SOI CMOS

Abstract

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Conference

Keywords

ASJC Scopus subject areas

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