A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Dajiang Zhou*, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)


8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline; 2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable; and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Number of pages2
Publication statusPublished - 2012
Externally publishedYes
Event59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
Duration: 2012 Feb 192012 Feb 23


Other59th International Solid-State Circuits Conference, ISSCC 2012
Country/TerritoryUnited States
CitySan Francisco, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


Dive into the research topics of 'A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications'. Together they form a unique fingerprint.

Cite this