A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Dajiang Zhou; Jinjia Zhou; Jiayi Zhu; Peilin Liu; Satoshi Goto

doi:10.1109/ISSCC.2012.6176985

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Dajiang Zhou^*, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Citations (Scopus)

Abstract

8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline; 2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable; and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages	224-225
Number of pages	2
Volume	55
DOIs	https://doi.org/10.1109/ISSCC.2012.6176985
Publication status	Published - 2012
Externally published	Yes
Event	59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States Duration: 2012 Feb 19 → 2012 Feb 23

Other

Other	59th International Solid-State Circuits Conference, ISSCC 2012
Country/Territory	United States
City	San Francisco, CA
Period	12/2/19 → 12/2/23

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/ISSCC.2012.6176985

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Zhou, D, Zhou, J, Zhu, J, Liu, P & Goto, S 2012, A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 55, 6176985, pp. 224-225, 59th International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, United States, 12/2/19. https://doi.org/10.1109/ISSCC.2012.6176985

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abstract = "8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline; 2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable; and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders.",

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AU - Goto, Satoshi

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A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

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