A 333MHz random cycle DRAM using the floating body cell

Kosuke Hatsuda; Katsuyuki Fujita; Takashi Ohsawa

doi:10.1109/CICC.2005.1568656

A 333MHz random cycle DRAM using the floating body cell

Kosuke Hatsuda^*, Katsuyuki Fujita, Takashi Ohsawa

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.

Original language	English
Title of host publication	Proceedings of the IEEE 2005 Custom Integrated Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	259-262
Number of pages	4
ISBN (Print)	0780390237, 9780780390232
DOIs	https://doi.org/10.1109/CICC.2005.1568656
Publication status	Published - 2005
Externally published	Yes
Event	IEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States Duration: 2005 Sept 18 → 2005 Sept 21

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2005
ISSN (Print)	0886-5930

Other

Other	IEEE 2005 Custom Integrated Circuits Conference
Country/Territory	United States
City	San Jose, CA
Period	05/9/18 → 05/9/21

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2005.1568656

Cite this

A 333MHz random cycle DRAM using the floating body cell. / Hatsuda, Kosuke; Fujita, Katsuyuki; Ohsawa, Takashi.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2005. p. 259-262 1568656 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hatsuda, K, Fujita, K & Ohsawa, T 2005, A 333MHz random cycle DRAM using the floating body cell. in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference., 1568656, Proceedings of the Custom Integrated Circuits Conference, vol. 2005, Institute of Electrical and Electronics Engineers Inc., pp. 259-262, IEEE 2005 Custom Integrated Circuits Conference, San Jose, CA, United States, 05/9/18. https://doi.org/10.1109/CICC.2005.1568656

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AB - A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.

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A 333MHz random cycle DRAM using the floating body cell

Abstract

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