A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

Tomohisa Wada; Toshihiko Hirose; Hirofumi Shinohara; Yuji Kawai; Kojiro Yuzuriha; Yoshio Kohno; Shimpei Kayano

doi:10.1109/JSSC.1987.1052806

A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

Tomohisa Wada, Toshihiko Hirose, Hirofumi Shinohara, Yuji Kawai, Kojiro Yuzuriha, Yoshio Kohno, Shimpei Kayano

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs.

Original language	English
Pages (from-to)	727-732
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	22
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1987.1052806
Publication status	Published - 1987 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1987.1052806

Cite this

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abstract = "This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs.",

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AU - Wada, Tomohisa

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AU - Shinohara, Hirofumi

AU - Kawai, Yuji

AU - Yuzuriha, Kojiro

AU - Kohno, Yoshio

AU - Kayano, Shimpei

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AB - This paper will describe a 128-kbit word × 8-bit CMOS SRAM with an access time of 34 ns and a standby current of 2 µA. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-µm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transistion detection (ATD) are used. This RAM has a “flash-clear” function in which logical zero's are written into all memory cells in less than 1 μs.

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A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon

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