TY - JOUR
T1 - A 35 ns 16K NMOS Static RAM
AU - Anami, Kenji
AU - Yoshimoto, Masahiko
AU - Shinohara, Hirofumi
AU - Hirata, Yoshihiro
AU - Harada, Hiroshi
AU - Nakano, Takao
PY - 1982/10
Y1 - 1982/10
N2 - An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.
AB - An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.
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U2 - 10.1109/JSSC.1982.1051824
DO - 10.1109/JSSC.1982.1051824
M3 - Article
AN - SCOPUS:0020193696
SN - 0018-9200
VL - 17
SP - 815
EP - 820
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 5
ER -