A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Yu Hong; Peilin Liu; Hang Zhang; Zongyuan You; Dajiang Zhou; Satoshi Goto

doi:10.1109/SOCDC.2009.5423878

A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Yu Hong^*, Peilin Liu, Hang Zhang, Zongyuan You, Dajiang Zhou, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.

Original language	English
Title of host publication	2009 International SoC Design Conference, ISOCC 2009
Pages	71-74
Number of pages	4
DOIs	https://doi.org/10.1109/SOCDC.2009.5423878
Publication status	Published - 2009
Event	2009 International SoC Design Conference, ISOCC 2009 - Busan Duration: 2009 Nov 22 → 2009 Nov 24

Other

Other	2009 International SoC Design Conference, ISOCC 2009
City	Busan
Period	09/11/22 → 09/11/24

Keywords

CABAC
H.264
Level 5.1

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SOCDC.2009.5423878

Cite this

@inproceedings{c64aed9c52444f40ae2b0320fe536674,

title = "A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications",

abstract = "This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.",

keywords = "CABAC, H.264, Level 5.1",

author = "Yu Hong and Peilin Liu and Hang Zhang and Zongyuan You and Dajiang Zhou and Satoshi Goto",

year = "2009",

doi = "10.1109/SOCDC.2009.5423878",

language = "English",

isbn = "9781424450343",

pages = "71--74",

booktitle = "2009 International SoC Design Conference, ISOCC 2009",

note = "2009 International SoC Design Conference, ISOCC 2009 ; Conference date: 22-11-2009 Through 24-11-2009",

}

TY - GEN

T1 - A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

AU - Hong, Yu

AU - Liu, Peilin

AU - Zhang, Hang

AU - You, Zongyuan

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.

AB - This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.

KW - CABAC

KW - H.264

KW - Level 5.1

UR - http://www.scopus.com/inward/record.url?scp=77951448353&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951448353&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2009.5423878

DO - 10.1109/SOCDC.2009.5423878

M3 - Conference contribution

AN - SCOPUS:77951448353

SN - 9781424450343

SP - 71

EP - 74

BT - 2009 International SoC Design Conference, ISOCC 2009

T2 - 2009 International SoC Design Conference, ISOCC 2009

Y2 - 22 November 2009 through 24 November 2009

ER -

A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Abstract

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this