A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi; Katsumi Dosaka; Takahiro Komatsu; Yoshinori Inoue; Masaki Kumanoya; Youichi Tobita; Hideki Genjyo; Masao Nagatomo; Tsutomu Yoshihara

doi:10.1109/4.62131

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi^*, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

Original language	English
Pages (from-to)	1112-1117
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	25
Issue number	5
DOIs	https://doi.org/10.1109/4.62131
Publication status	Published - 1990 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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abstract = "The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.",

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AU - Konishi, Yasuhiro

AU - Dosaka, Katsumi

AU - Komatsu, Takahiro

AU - Inoue, Yoshinori

AU - Kumanoya, Masaki

AU - Tobita, Youichi

AU - Genjyo, Hideki

AU - Nagatomo, Masao

AU - Yoshihara, Tsutomu

PY - 1990/10

Y1 - 1990/10

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AB - The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

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A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

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