A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi*, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

Original languageEnglish
Pages (from-to)1112-1117
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 1990 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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