TY - GEN
T1 - A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption
AU - Yoshida, Yutaka
AU - Kamei, Tatsuya
AU - Hayase, Kiyoshi
AU - Shibahara, Shinichi
AU - Nishii, Osamu
AU - Hattori, Toshihiro
AU - Hasegawa, Atsushi
AU - Takada, Masashi
AU - Irie, Naohiko
AU - Uchiyama, Kunio
AU - Odaka, Toshihiko
AU - Takada, Kiwamu
AU - Kimura, Keiji
AU - Kasahara, Hironori
PY - 2007
Y1 - 2007
N2 - A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.
AB - A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.
UR - http://www.scopus.com/inward/record.url?scp=34548855675&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548855675&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2007.373607
DO - 10.1109/ISSCC.2007.373607
M3 - Conference contribution
AN - SCOPUS:34548855675
SN - 1424408539
SN - 9781424408535
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 100
EP - 102
BT - 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Y2 - 11 February 2007 through 15 February 2007
ER -