A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC

Dajiang Zhou; Gang He; Wei Fei; Zhixiang Chen; Jinjia Zhou; Satoshi Goto

doi:10.1109/VLSIC.2012.6243836

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC

Dajiang Zhou^*, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, Satoshi Goto

^*Corresponding author for this work

Information, Production and Systems Research Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz.

Original language	English
Title of host publication	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages	154-155
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243836
Publication status	Published - 2012
Event	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI Duration: 2012 Jun 13 → 2012 Jun 15

Other

Other	2012 Symposium on VLSI Circuits, VLSIC 2012
City	Honolulu, HI
Period	12/6/13 → 12/6/15

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VLSIC.2012.6243836

Cite this

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title = "A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC",

abstract = "An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz.",

author = "Dajiang Zhou and Gang He and Wei Fei and Zhixiang Chen and Jinjia Zhou and Satoshi Goto",

year = "2012",

doi = "10.1109/VLSIC.2012.6243836",

language = "English",

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AU - He, Gang

AU - Fei, Wei

AU - Chen, Zhixiang

AU - Zhou, Jinjia

AU - Goto, Satoshi

PY - 2012

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N2 - An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz.

AB - An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680x4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2mW at 0.8V and 9MHz.

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DO - 10.1109/VLSIC.2012.6243836

M3 - Conference contribution

AN - SCOPUS:84866611334

SN - 9781467308458

SP - 154

EP - 155

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012

Y2 - 13 June 2012 through 15 June 2012

ER -

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC

Abstract

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ASJC Scopus subject areas

UN SDGs

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