A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii; M. Yabuuchi; Y. Tsukamoto; S. Ohbayashi; Y. Oda; K. Usui; T. Kawamura; N. Tsuboi; T. Iwasaki; K. Hashimoto; H. Makino; H. Shinohara

doi:10.1109/VLSIC.2008.4586011

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii^*, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

101 Citations (Scopus)

Abstract

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

Original language	English
Title of host publication	2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	212-213
Number of pages	2
ISBN (Print)	9781424418053
DOIs	https://doi.org/10.1109/VLSIC.2008.4586011
Publication status	Published - 2008
Externally published	Yes
Event	2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States Duration: 2008 Jun 18 → 2008 Jun 20

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
Country/Territory	United States
City	Honolulu, HI
Period	08/6/18 → 08/6/20

Keywords

45nm
6T
8T
CMOS
DVFS
SRAM
Stability

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2008.4586011

Cite this

Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H., & Shinohara, H. (2008). A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC (pp. 212-213). Article 4586011 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2008.4586011

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. / Nii, K.; Yabuuchi, M.; Tsukamoto, Y. et al.
2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. Institute of Electrical and Electronics Engineers Inc., 2008. p. 212-213 4586011 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nii, K, Yabuuchi, M, Tsukamoto, Y, Ohbayashi, S, Oda, Y, Usui, K, Kawamura, T, Tsuboi, N, Iwasaki, T, Hashimoto, K, Makino, H & Shinohara, H 2008, A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. in 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC., 4586011, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 212-213, 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC, Honolulu, HI, United States, 08/6/18. https://doi.org/10.1109/VLSIC.2008.4586011

Nii K, Yabuuchi M, Tsukamoto Y, Ohbayashi S, Oda Y, Usui K et al. A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. Institute of Electrical and Electronics Engineers Inc. 2008. p. 212-213. 4586011. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2008.4586011

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abstract = "We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.",

keywords = "45nm, 6T, 8T, CMOS, DVFS, SRAM, Stability",

author = "K. Nii and M. Yabuuchi and Y. Tsukamoto and S. Ohbayashi and Y. Oda and K. Usui and T. Kawamura and N. Tsuboi and T. Iwasaki and K. Hashimoto and H. Makino and H. Shinohara",

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AU - Nii, K.

AU - Yabuuchi, M.

AU - Tsukamoto, Y.

AU - Ohbayashi, S.

AU - Oda, Y.

AU - Usui, K.

AU - Kawamura, T.

AU - Tsuboi, N.

AU - Iwasaki, T.

AU - Hashimoto, K.

AU - Makino, H.

AU - Shinohara, H.

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N2 - We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

AB - We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

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KW - 6T

KW - 8T

KW - CMOS

KW - DVFS

KW - SRAM

KW - Stability

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ER -

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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