A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

S. Ishikura; M. Kurumada; T. Terano; Y. Yamagami; N. Kotani; K. Satomi; K. Nii; M. Yabuuchi; Y. Tsukamoto; S. Ohbayashi; T. Oashi; H. Makino; H. Shinohara; H. Akamatsu

doi:10.1109/VLSIC.2007.4342740

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

S. Ishikura^*, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, H. Akamatsu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].

Original language	English
Title of host publication	2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	254-255
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2007.4342740
Publication status	Published - 2007
Externally published	Yes
Event	2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan Duration: 2007 Jun 14 → 2007 Jun 16

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2007 Symposium on VLSI Circuits, VLSIC
Country/Territory	Japan
City	Kyoto
Period	07/6/14 → 07/6/16

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2007.4342740

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Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H., & Akamatsu, H. (2007). A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 254-255). Article 4342740 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2007.4342740

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues. / Ishikura, S.; Kurumada, M.; Terano, T. et al.
2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. 2007. p. 254-255 4342740 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ishikura, S, Kurumada, M, Terano, T, Yamagami, Y, Kotani, N, Satomi, K, Nii, K, Yabuuchi, M, Tsukamoto, Y, Ohbayashi, S, Oashi, T, Makino, H, Shinohara, H & Akamatsu, H 2007, A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues. in 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 4342740, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 254-255, 2007 Symposium on VLSI Circuits, VLSIC, Kyoto, Japan, 07/6/14. https://doi.org/10.1109/VLSIC.2007.4342740

Ishikura S, Kurumada M, Terano T, Yamagami Y, Kotani N, Satomi K et al. A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. 2007. p. 254-255. 4342740. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2007.4342740

@inproceedings{243c32299196476cbe5c4df793c0d6d9,

title = "A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues",

abstract = "We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].",

author = "S. Ishikura and M. Kurumada and T. Terano and Y. Yamagami and N. Kotani and K. Satomi and K. Nii and M. Yabuuchi and Y. Tsukamoto and S. Ohbayashi and T. Oashi and H. Makino and H. Shinohara and H. Akamatsu",

year = "2007",

doi = "10.1109/VLSIC.2007.4342740",

language = "English",

isbn = "9784900784048",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "254--255",

booktitle = "2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers",

note = "2007 Symposium on VLSI Circuits, VLSIC ; Conference date: 14-06-2007 Through 16-06-2007",

}

TY - GEN

T1 - A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

AU - Ishikura, S.

AU - Kurumada, M.

AU - Terano, T.

AU - Yamagami, Y.

AU - Kotani, N.

AU - Satomi, K.

AU - Nii, K.

AU - Yabuuchi, M.

AU - Tsukamoto, Y.

AU - Ohbayashi, S.

AU - Oashi, T.

AU - Makino, H.

AU - Shinohara, H.

AU - Akamatsu, H.

PY - 2007

Y1 - 2007

N2 - We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].

AB - We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].

UR - http://www.scopus.com/inward/record.url?scp=39749119399&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=39749119399&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2007.4342740

DO - 10.1109/VLSIC.2007.4342740

M3 - Conference contribution

AN - SCOPUS:39749119399

SN - 9784900784048

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 254

EP - 255

BT - 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers

T2 - 2007 Symposium on VLSI Circuits, VLSIC

Y2 - 14 June 2007 through 16 June 2007

ER -

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

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