TY - GEN
T1 - A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications
AU - Zhou, Dajiang
AU - Wang, Shihao
AU - Sun, Heming
AU - Zhou, Jianbin
AU - Zhu, Jiayi
AU - Zhao, Yijin
AU - Zhou, Jinjia
AU - Zhang, Shuping
AU - Kimura, Shinji
AU - Yoshimura, Takeshi
AU - Goto, Satoshi
N1 - Publisher Copyright:
© 2016 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/2/23
Y1 - 2016/2/23
N2 - 8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, the latest high-efficiency video coding standard (H.265/HEVC) greatly enhances the feasibility of 8K by doubling the compression ratio. Implementation of such codecs is a challenge, owing to ultra-high throughput requirements and increased complexity per pixel. The former corresponds to up to 10b/pixel, 7680×4320pixels/frame and 120fps - 80× larger than 1080p HD. The latter comes from the new features of HEVC relative to its predecessor H.264/AVC. The most challenging of them is the enlarged and highly variable-size coding/prediction/transform units (CU/PU/TU), which significantly increase: 1) the requirement for on-chip memory as pipeline buffers, 2) the difficulty in maintianing pipeline utilization, and 3) the complexity of inverse transforms (IT). This paper presents an HEVC decoder chip supporting 8K Ultra HD, featuring a 16pixel/cycle true-variable-block-size system pipeline. The pipeline: 1) saves on-chip memory with a novel block-in-block-out (BIBO) queue system and a parameter delivery network, and 2) allows high design efficiency and utilization of processing components through local synchronization. Key optimizations at the component level are also presented.
AB - 8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, the latest high-efficiency video coding standard (H.265/HEVC) greatly enhances the feasibility of 8K by doubling the compression ratio. Implementation of such codecs is a challenge, owing to ultra-high throughput requirements and increased complexity per pixel. The former corresponds to up to 10b/pixel, 7680×4320pixels/frame and 120fps - 80× larger than 1080p HD. The latter comes from the new features of HEVC relative to its predecessor H.264/AVC. The most challenging of them is the enlarged and highly variable-size coding/prediction/transform units (CU/PU/TU), which significantly increase: 1) the requirement for on-chip memory as pipeline buffers, 2) the difficulty in maintianing pipeline utilization, and 3) the complexity of inverse transforms (IT). This paper presents an HEVC decoder chip supporting 8K Ultra HD, featuring a 16pixel/cycle true-variable-block-size system pipeline. The pipeline: 1) saves on-chip memory with a novel block-in-block-out (BIBO) queue system and a parameter delivery network, and 2) allows high design efficiency and utilization of processing components through local synchronization. Key optimizations at the component level are also presented.
UR - http://www.scopus.com/inward/record.url?scp=84962796424&partnerID=8YFLogxK
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U2 - 10.1109/ISSCC.2016.7418009
DO - 10.1109/ISSCC.2016.7418009
M3 - Conference contribution
AN - SCOPUS:84962796424
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 266
EP - 268
BT - 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
Y2 - 31 January 2016 through 4 February 2016
ER -